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c o p y r i g h t ! 2 0 0 4 i a 1 8 6 e m / i a 1 8 8 e m 8/16-bit microcontrollers data sheet
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 contents feat ures ............................................................................................................................... ....................... 4 descri pti o n ............................................................................................................................... ................ 5 b u s i n t e r f a c e a n d c o n t r o l ................................................................................................................ 7 peripheral control and registers .................................................................................................. 7 clock and power management .................................................................................................... 49 system cloc ks ............................................................................................................................... ........... 49 power-save mode ............................................................................................................................... ..... 50 i n i t i a l i z a t i o n a n d r e s e t ............................................................................................................................. 50 reset configuration register ................................................................................................................... 50 ch i p -s e l e c t s ............................................................................................................................... .............. 50 ch i p -s e l e c t t i m i n g ............................................................................................................................... ... 50 ready and wait-state p r ogramm i ng ........................................................................................................ 50 c h i p - s e l e c t o v e r l a p ............................................................................................................................... .. 51 upper memory chip select ..................................................................................................................... 52 low mem ory chip selec t ........................................................................................................................ 52 midrange mem ory chip selects .............................................................................................................. 52 p e r i p h e r a l c h i p s e l e c t s ............................................................................................................................ 52 refresh control ............................................................................................................................... ......... 53 interrupt control ............................................................................................................................... ....... 53 interrupt types ............................................................................................................................... ...... 54 interrupt table notes ........................................................................................................................... 55 t i m e r c o n t r o l ............................................................................................................................... ............ 55 direct m e mory access (dma) ................................................................................................................ 56 dma operation ............................................................................................................................... ........ 56 dma channel control registers ......................................................................................................... 56 dma priority ............................................................................................................................... ........ 57 a s y n c h r o n o u s s e r i a l p o r t ............................................................................................................... 58 synchronous serial port .................................................................................................................. 58 p r o g r a m m a b l e i / o ( p i o ) ................................................................................................................ 59 pin des c riptions ............................................................................................................................... ... 60 i n s t r u c t i o n s e t s u m m a r y ................................................................................................................ 71 key to abbreviations used instruction summ ary table ......................................................................... 85 a b s o l u t e m a x i m u m r a t i n g s ......................................................................................................... 90 d c c h a r a c t e r i s t i c s o v e r c o m m e r c i a l o p e r a t i n g r a n g e s .............................................. 90 ac characteris tics over comm er cial operating ranges (40 mhz) ........................................................... 91 w a v e f o r m s ............................................................................................................................... .............. 94 a l p h a b e t i c k e y t o w a v e f o r m p a r a m e t e r s ................................................................................................ 94 n u m e r i c k e y t o w a v e f o r m p a r a m e t e r s ................................................................................................... 95 read cycle tim i ng ............................................................................................................................... ... 97 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 w r i t e c y c l e ............................................................................................................................... ............... 98 w r i t e c y c l e t i m i n g ............................................................................................................................... .. 99 psr am r e ad c ycle ............................................................................................................................... 100 psram read cycle tim i ng .................................................................................................................. 101 psram w r ite cycle .............................................................................................................................. 102 psram w r ite cycle tim i ng ................................................................................................................. 103 psram re fresh cycle .......................................................................................................................... 104 psram re fresh cycle .......................................................................................................................... 104 interrupt acknowledge cycle ................................................................................................................ 105 interrupt acknowledge cycle tim i ng ................................................................................................... 106 software halt cycle ............................................................................................................................... 107 software halt cycle timing .................................................................................................................. 107 clock ?active mode ............................................................................................................................. 108 clock ?power-save mode .................................................................................................................... 108 c l o c k t i m i n g ............................................................................................................................... .......... 108 srdy ?synchronous ready ..................................................................................................................... 109 ardy - asynchronous ready .................................................................................................................. 109 p e r i p h e r a l s ............................................................................................................................... ............... 109 ready and peripheral t i m i ng ................................................................................................................. 109 r e s e t 1 ............................................................................................................................... ..................... 110 r e s e t 2 ............................................................................................................................... ..................... 110 bus hold enter i ng ............................................................................................................................... ... 111 bus hold leaving ............................................................................................................................... ... 111 reset and b us hold timing ................................................................................................................... 111 synchronous serial interface ................................................................................................................. 112 synchronous serial in terface tim i ng .................................................................................................... 112 ia186em 100-pin pqfp ........................................................................................................................... 113 ia186em tqfp 100-pin ........................................................................................................................... 116 ia188em 100-pin pqfp ........................................................................................................................... 119 ia188em 100-pin tqfp ........................................................................................................................... 122 physical dim e nsions ............................................................................................................................... ... 125 p q f p 1 0 0 ............................................................................................................................... ................ 125 tqfp 100 ............................................................................................................................... .............. 127 ordering information ...................................................................................................................... 128 e r r a t a ............................................................................................................................... ........................ 129 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p l e a s e n o t e i n c l u d e d i n t h e o r d e r i n g i n form ation section on page 128 o f t h i s m a n u a l a r e e n h a n c e d r o h s - c o m p l i a n t versions of the ia186 and ia188 fa mily of m i crocont rollers. however, standard packaged or non rohs- com pliant versions of the ia186 and ia188 m i crocontrollers are still available. f e a t u r e s " p i n - f o r - p i n c o m p a t i b l e w i t h a m d # am 186em/ 188em devices " a l l f e a t u r e s a r e r e t a i n e d , i n c l u d i n g : " pll allowing sam e crystal/system clock frequency " 8086/8088 instruction set with additiona l 186 instruction set extensions " p ro g ra m m a b l e i n t e rrupt controller " two dma c hannels " t h r e e 1 6 - b i t t i m e r s " p r o g r a m m a b l e c h i p s e l e c t l o g i c a n d w a i t - s t a t e g e n e r a t o r " d e d i c a t e d w a t c h d o g t i m e r " two independent asynchronous serial ports (uarts) o dma capability o h a rd w a re fl o w c o n t ro l o 7-, 8-, or 9-bit data capability " p u l s e w i d t h d e m o d u l a t o r fe a t u re " u p t o 3 2 p ro g ra m m a b l e i/ o p i n s (p io ) " pseudo-static/dynam i c ram controller " fully static cmos design " 4 0 m h z o p e r a t i o n a t i n d u s t r i a l o p e r a t i n g c o n d i t i o n s " +5 vdc power supply " available packages: o 100-pin thin quad flat pack (tqfp) o 100-pin plastic quad flat pack (pqfp) the ia186em/188em is a for m , fit and function repla cem ent for the original advanced micro devices # am 186em/ 188em fa m ily of m i crocontrollers. innova sic produces replacem ent ics using its miles t m , o r m a n a g e d i c l i f e t i m e e x t e n s i o n s y s t e m c l o n i n g technology. this technology produces replacem ent i c s f a r m o r e c o m p l e x t h a n " e m u l a t i o n " w h i l e e n s u r i n g t h e y a r e c o m p a t i b l e w i t h t h e o r i g i n a l i c . miles t m c a ptures the design of a clone so it can be produced even as silicon technology advances. miles t m also verifies the clone against the original ic so that even the "u n d o c u m e n t e d f e a t u r e s " a r e duplicated. this data sheet contains prelim inary inform ati on for the ia186em/188em. the complete data sheet which docum ents all necessary engineering inform a t i o n a b o u t t h e i a 1 8 6 e m / 1 8 8 e m including functional a n d i / o d e s c r i p t i o n s , e l e c t r i c a l c h a r a c t e r i s t i c s , a n d a p p l i c a b l e t i m i n g w i l l b e a v a i l a b l e w h e n t h e d e v i c e n e a r s c o m p l e t i o n . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 d e s c r i p t i o n the ia186em/188em fam ily of m i c r ocont rollers replaces obsolete amd # a m 1 8 6 e m / 1 8 8 e m d e v i c e s , allowing custom ers to retain existing board designs, s o f t w a r e c o m p i l e r s / a s s e m b l e r s a n d e m u l a t i o n t o o l s , thereby avoiding expensive redesign efforts. the ia186em/188em m i crocontrollers are an upgrade for the 80c186/188 m i crocontroller designs, with integrated peripherals to provide increased functionality and reduce system costs. the innovasic devices are created to satisfy requirem ents of em bedde d products designed for telecommunications, office a u t o m a t i o n a n d s t o ra g e a n d i n d u s t ri a l c o n t ro l s . a block diagram of the ia186em/188em m i crocontroller is depicted in f i g u r e 1 . the ia186em/188em m i c r o c o n t r o l l e r c o n s i s t s o f t h e f o l l o w i n g f u n c t i o n a l b l ock s , with brief discussions of each afterwards. " bus interface and control " p e r i p h e r a l c o n t r o l a n d r e g i s t e r s " chip selects and control " programm a ble i/o " clock and power managem e nt " direct m e mory access (dma) " interrupt controller " t i m e r s " asynchronous serial ports " synchronous serial in terface. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i n s t r u c t i o n d e c o d e a n d e x e c u t i o n c l o c k a n d p o w e r m a n a g e m e n t d i r e c t m e m o r y a c c e s s i n t e r r u p t c o n t r o l l e r t i m e r s a s y n c h r o n o u s s e r i a l p o r t s y n c h r o n o u s s e r i a l p o r t b u s i n t e r f a c e & c o n t r o l c h i p s e l e c t s a n d c o n t r o l p e r i p h e r a l c o n t r o l a n d r e g i s t e r s p r o g r a m m a b l e i / o a d [ 1 5 : 0 ] a l e d e n _ n w r _ n w l b _ n w h b _ n r d _ n u z i _ n s 6 / c l k d i v 2 _ n h o l d h l d a d e n _ n / d s _ n d t / r _ n s r d y a r d y s 2 _ n - s 0 _ n l c s _ n / o n c e 0 _ n u c s _ n / o n c e 1 _ n p c s 5 _ n / a 1 m c s 3 _ n / r f s h _ n p c s 6 _ n / a 2 a [ 1 9 : 0 ] m c s 2 _ n - m c s 0 _ n p c s 3 _ n - p c s 0 _ n p i o [ 3 1 : 0 ] c l k o u t a c l k o u t b d r q 0 d r q 1 i n t 4 i n t 3 / i n t a 1 _ n / i r q i n t 2 / i n t a 0 _ n i n t 1 / s e l e c t _ n i n t 0 n m i t x d 0 r x d 0 c t s 0 _ n / e n r x 0 _ n r t s 0 _ n / r t r 0 _ n s c l k s d e n 0 s d e n 1 s d a t a t m r i n 0 t m r o u t 0 t m r i n 1 t m r o u t 1 v c c g n d r e s _ n f i g u r e 1 . i a 1 8 6 / 8 8 e m b l o c k d i a g r a m n o t e see pin descriptions for pins that sh are other functions with pio pins. pwd, int5, int6, rts1_n/rtr1_n, a n d cts1_n/enrx1_n a r e m u l t i p l e x e d with int2_n/inta0_n, drq0_n, drq0_n, pcs3_n, a n d pcs2_n r e s p e c t i v e l y . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 b u s i n t e r f a c e a n d c o n t r o l bu s in t e rfa c e a n d co n t ro l (bic) m a n a g e s a l l a c c e s s e s t o e x t e rn a l m e m o ry a n d e x t e rn a l p e ri p h e ra l s . t h e s e p e r i p h e r a l s m a y b e m a p p e d e i t h e r i n m e m o r y s p a c e o r i/ o s p a c e . t h e bic s u p p o rt s b o t h m u l t i p l e x e d a n d n o n - m u l t i p l e x e d b u s o p e r a t i o n s . m u l t i p l e x e d a d d r e s s a n d d a t a a r e p r o v i d e d o n t h e ad [15:0] b u s , w h i l e a n o n -m u l t i p l e x e d a d d re s s i s p ro v i d e d o n t h e a [19:0] bus. the a bus provides address infor m ation for the e n t i r e b u s c y c l e ( t 1 - t 4 ) , w h i l e t h e ad b u s p ro v i d e s a d d re s s i n fo rm a t i o n o n l y during the first (t1) phase of the bus cycle. for m ore details regarding bus cycles, see the ac wavefor m s at the end of this datasheet. the ia186em m i crocontroller provides two signals that serv e as byte write enables: write high byte ( w h b _ n ) and write low byte ( w l b _ n ). obviously, the ia188em m i crocon t r o l l e r r e q u i r e s only a single w r i t e b y t e ( w b _ n ) signal to support its 8-bit data bus. w h b _ n is the logical or of the bhe_n and w r _ n . w l b _ n is the logical or of a d 0 and w r _ n . w l b _ n is the logical or of a d 0 and w r _ n . w b _ n is low whenever a byte is writte n to the ia188em data bus ad[7:0]. t h e b y t e w r i t e e n a b l e s a r e d r i v e n i n c o n j u n c t i o n w i t h t h e n o n - m u l t i p l e x e d a d d r e s s bus a [ 1 9 : 0 ] t o f a c i l i t a t e m e e t i n g t h e t i m i n g r e quirem ents of common srams. the bic also provides support for pseudo-static ra m (psram) devices. psram is supported in the l o w e r c h i p s e l e c t ( lcs_n ) area only. in order to support psram, th e ch i p s e l e c t s a n d co n t ro l (cs c ) m u s t be appropriately programmed. for deta ils regarding this operation, see chip selects . p e r i p h e r a l c o n t r o l a n d r e g i s t e r s the on-chip peripherals in the ia186em/188em m i cr o c o n t r o l l e r a r e c o n t r o l l e d from a 256-byte block of internal registers. although these re gisters are actually located i n t h e p e r i p h e r a l s t h e y c o n t r o l , t h e y a r e a d d re s s e d w i t h i n a s i n g l e 2 5 6 -b y t e b l o c k o f i/ o s p a c e d and are therefore treated as a f unctional un it for the purposes of this docum ent. a m a p of these regist ers is depicted in t a b l e 1 . all write operations perf orm e d on the ia188em should be 8-bit writ es, w hich will stil l r e s u l t i n 1 6 - b i t data transfers to the peripheral contro l block (p cb) register even if the na m e d register is an 8-bit register. any read perform e d to the pcb regi sters should be word reads. code w r i t t e n w i t h t h ese points in m i nd will run correctly on bo th the ia186 em and ia188em. however, unpredictable behavior will result in bo th the ia186em and ia188em processors if unaligned read and write accesses are perform e d. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 regis t er nam e offset p erip h era l c o n tr o l blo ck r eg isters p c b r e lo c a tio n r e g is te r f e h reset conf iguration reg i ster f6h p r o c e s s o r r e l e a s e l e v e l r e g i s t e r f 4 h p o w e r - s a v e c o n t r o l r e g i s t e r f 0 h e n a b l e r c u r e g i s t e r e 4 h clock prescaler register e2h m e m o r y p a r t i t i o n r e g i s t e r e 0 h d m a r e g i s t e r s dma1 control register dah dma1 transfer count reg i ster d8h dma1 destination address high register d6h dma1 destination address low register d4h dma1 source address high register d2h dma1 source address low register d0h dma0 control register cah dma0 transfer count reg i ster c8h dma0 destination address high register c6h dma0 destination address low register c4h dma0 source address high register c2h dma0 source address low register c0h c h ip -s elect r eg isters pcs_n and mcs_ n auxiliar y r e gister a8h mid-range memory chip-select reg i ster a6h p e r i p h e r a l c h i p - s e l e c t r e g i s t e r a 4 h low-memor y c hip-select r e gis t er a2h upper-memor y chip-select r e g i ster a0h asynchr o nous serial p o rt register serial port baud rate divisor register 88h serial port receive reg i ster 86h serial port trans m it register 84h s e r ia l p o r t s ta tu s r e g is te r 8 2 h s e r i a l p o r t c o n t r o l r e g i s t e r 8 0 h pio regis t ers pio data 1 register 7ah pio direction 1 register 78h pio mode 1 reg i ster 76h pio data 0 register 74h pio direction 0 register 72h pio mode 0 reg i ster 70h regis t er nam e offset timer regis t e rs timer 2 mode & control register 66h timer 2 max co unt compare a register 62h t i m e r 2 c o u n t r e g i s t e r 6 0 h timer 1 mode & cont r o l r e g i s t e r 5 e h timer 1 max co unt compare b register 5ch timer 1 max co unt compare a register 5ah t i m e r 1 c o u n t r e g i s t e r 5 8 h timer 0 mode & control register 56h timer 0 max co unt compare b register 54h timer 0 max co unt compare a register 52h t i m e r 0 c o u n t r e g i s t e r 5 0 h interrupt re gisters s e r ia l p o r t 0 i n te r r u p t c o n tr o l r e g is te r 4 4 h watchdog timer cont r o l r e g i s t e r 4 2 h i n t 4 i n t e r r u p t c o n t r o l r e g i s t e r 4 0 h i n t 3 i n t e r r u p t c o n t r o l r e g i s t e r 3 e h i n t 2 i n t e r r u p t c o n t r o l r e g i s t e r 3 c h i n t 1 i n t e r r u p t c o n t r o l r e g i s t e r 3 a h i n t 0 i n t e r r u p t c o n t r o l r e g i s t e r 3 8 h dma1 interrupt control register 36h dma0 interrupt control register 34h timer interrupt control r e gister 32h i n te r r u p t s ta tu s r e g is te r 3 0 h i n t e r r u p t r e q u e s t r e g i s t e r 2 e h i n - s e r v i c e r e g i s t e r 2 c h p r i o r i t y m a s k r e g i s t e r 2 a h interrupt mask register 28h p o ll s ta tu s r e g is te r 2 6 h poll register 24h e n d - o f - i n t e r r u p t ( e o i ) r e g i s t e r 2 2 h interrupt vector register 20h sync hronous serial p o rt re gister s y n c h r o n o u s s e r i a l r e c e i v e r e g i s t e r 1 8 h s y nchronous ser i al transmit 0 r e gister 16h s y nchronous ser i al transmit 1 r e gister 14h s y n c h r o n o u s s e r i a l e n a b l e r e g i s t e r 1 2 h s y nchronous ser i al status r e gister 10h table 1. map of peripher a l contr o l regis t ers 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 relreg (0feh) - the peripheral c ontrol block r e l o c a t i o n r e g i s t e r m a p s t h e e n t i r e p e r i p h e r a l c o n t r o l b l o c k r e g i s t e r b a n k t o e i t h er i/o or m e mory space. in addi t i o n , r e l r e g c o n t a i n s a b i t w h i c h p l a c e s t h e i n t e r r u p t c o n t r o l l e r i n e i t h e r m a s t e r o r s l a v e m o d e . the relreg contains 20ffh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res s/mn res io/mn ra [19:8 ] r e s ( b i t 1 5 ) - r e s e r v e d . s/mn (bit 14) ?a 1 in this bit places the interrupt contro ller into slave m o de. w hen set to zero, the in t e rru p t co n t ro l l e r i s i n m a s t e r m o d e . r e s ( b i t 1 3 ) - r e s e r v e d . i o / m n ( b i t 1 2 ) - a 1 i n t h i s b i t m a p s t h e p e r i p h e r a l c ontrol block register bank into io space. when set to zero, the peripheral control bl o c k i s m a p p e d i n t o m e m o ry s p a c e . ra [19:8 ] ( bits 11-0) ?sets the base address (upper 12 bits) of the peripheral control block register bank. ra [7:0} default to zero. note that when bit 12 ( i o / m _ n ) i s a 1 , r a [19:16 ] are ignored. r e s c o n ( 0 f 6 h ) - t h e r e s e t c o n figuration register latches user-d e f i n e d i n f o r m a t i o n p r e s e n t a t s p e c i f i e d p i n s a t t h e ri s i n g e d g e o f re s e t . t h i s c o n t e n t s o f t h i s r e g i s t e r a r e r e a d - o n l y a n d r e m a i n v a l i d u n t i l the next reset. t h e r e s c o n c o n t a i n s u s e r - d e f i n e d i n f o r m a t i o n a t r e s e t . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r c [ 1 5 : 0 ] rc [15:0 ] ( bits 15-0) ?at the rising edge of reset, the values of specified pins ( ad [15:0] f o r t h e ia186es and { ao [15:8], ad [7:0] } fo r t h e ia 1 8 8 e m ) a re l a t c hed into this register. prl (0f4h) - t h e p r o c e s s o r r elease l evel register contains a code co rresponding to the latest processor production release. the prl i s a re a d -o n l y re g i s t e r the prl contains 0400h. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 prl [7:0 ] res prl [7:0 ] ( bits 15-8) ?the latest processor release level. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p r l v a l u e p r o c e s s o r r e l e a s e le v e l 0 1 h c 0 2 h d 03h e 04h f r e s (b i t s 7 -0 ) ?reserved. pdcon (0 f0h) - t h e power-save c o n trol register controls severa l m i scellaneous system i/o and t i m i n g f u n c t i o n s . the syscon contains 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p s e n r e s c b f c b d c a f c a d r e s f 2 f 1 f 0 psen (bit 15 ) w h e n s e t t o 1 , e n a b l e s t h e p o w e r - s a v e m ode causing the internal operating clock to be divided by the value in f2-f0 . e x t e r n a l i n t e r r u p t s o r i n t e r r upts from internal interrupts a u t o m a t i c a l l y c l e a r p s e n . software interrupts and exception do not clear p s e n . n o t e t h a t t h e v a l u e o f p s e n is not restored upon execu tion of an iret instruction. r e s ( b i t 1 4 - 1 2 ) re s e rv e d . t h e s e b i t s re a d b a c k a s z e ro s . cbf (bit 11 ) w h e n s e t t o 1 , t h e c l k o u t b output follows the input cr ystal (pll) frequency. w hen t h i s b i t i s 0 , t h e c l k o u tb f o l l o w s t h e i n t e r n a l c l o c k f r e q u e n c y a ft e r t h e c l o c k d i v i d e r. cbd ( bit 10) w h e n s e t t o 1 , t h e c l k o u t b output is pulled low. w hen this bit is 0, the c l k o u t b i s driven as an output per the c b f b i t . caf (bit 9 ) w h e n s e t t o 1 , t h e c l k o u t a output follows the input crysta l ( p l l ) f r e q u e n c y . w h e n t h i s b i t i s 0 , t h e c l k o u t a follows the internal clock frequency after the clock divider. cad ( bit 8) w h e n s e t t o 1 , t h e c l k o u t a output is pulled low. wh e n t h i s b i t i s 0 , t h e c l k o u ta is driven a s a n o u t p u t p e r t h e c b f b i t . r e s (b i t s 7 -3 ) ? reserved. these bits read back as zeros. f2-f0 (bits 2-0) ? these bits control the clock di vider as shown below. note that p s e n m u s t b e 1 f o r the clock divider to function. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 f2 f1 f0 divider factor 0 0 0 divide by 1 (2 0 ) 0 0 1 divide by 2 (2 1 ) 0 1 0 divide by 4 (2 2 ) 0 1 1 divide by 8 (2 3 ) 1 0 0 divide by 16 (2 4 ) 1 0 1 divide by 32 (2 5 ) 1 1 0 divide by 64 (2 6 ) 1 1 1 d i v i d e b y 1 2 8 ( 2 7 ) edram (0e4h) - t h e e nable rcu register provides control and status f or the refresh counter. the edram register cont ains 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 e 0 0 0 0 0 0 t [8:0 ] e ( b i t 1 5 ) ?when set to 1, the refr esh counter is enabled and m s c 3 _ n is configured to act as r f s h _ n . c l e a r i n g e clears the refresh counter and disables refresh requests. the refresh address is unaffected by clearing e . res (bits 14-9) ?reserved. these bits read back as 0. t [ 8 : 0 ] ( b i t s 8 - 0 ) ?thes e bits hold the current value of th e refresh counter. these bits are read-only. cdram (0e2h) - t h e c l o c k p re s c a l e r re g i s t e r d e t e rm i n e s t h e p e ri o d b e t w e e n re fre s h c y c l e s . t h e cd ra m re g i s t e r i s undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 rc [8:0 ] res (bits 15-9) ?reserved. these bits read back as 0. rc [8:0 ] (bits 8-0) ?these bits hold the clock count interv al between refresh cycles. this value should not be set to less than 18 ( 12h), else there would never be suffi cient bus cycles available for the p r o c e s s o r t o e x e c u t e c o d e . in power-save m ode, the refresh counter value shoul d be adjusted to account for the clock divider value in sy scon. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 mdram (0e0h) - t h e m em ory partition register holds the a19- a13 address bits of the 20-bit base refresh address. the mdram register cont ains 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 m [6:0 ] 0 0 0 0 0 0 0 0 0 m [6:0 ] (bits 15-9) ?upper bits corresponding to address bits a19-a13 of the 20-bit m e mory refresh a d d r e s s . t h e s e b i t s a r e n o t a v a i l a b l e o n t h e a 1 9 - a 0 bus. w hen using psram m ode, m 6 - m 0 m u s t b e p r o g r a m m e d t o 0 0 0 0 0 0 0 b . reserved [8:0 ] (bits 8-0 ) ? reserved. these bits read back as 0. d 1 c o n ( 0 d a h ) - d m a c o n t r o l r e g i s t e r s . d0con (0cah) d m a control registers control opera tion of the two dma channels. the d0con and d1con registers are undefined at reset, except st t h a t i s s e t t o 0 . 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 dm/i on ddec dinc sm/i on s d e c s i n c t c i n t s y n 1 - s y n 0 p t d r q r e s c h g s t b n / w dm/ion (bit 15) ? destination address space select selects m e mory or i/o space for the des tination address. when d m / i o i s s e t t o 1 , t h e d e s t i n a t i o n a d d r e s s i s i n m e m o r y s p a c e . w h e n s e t t o 0 , t h e destin ation address is in i/o space. ddec (bit 14 ) d e s t i n a t i o n d e c r e m e n t a u t o m a t i c a l l y d e c r em ents the destination ad dress after each t r a n s f e r w h e n s e t t o 1 . t h e a d d r e s s i s d e c r e m ented by 1 or 2, depending on the byte/word bit ( b n / w , bit 0). the address does not change if the incremen t a n d d e c r e m e n t b i t s a r e s e t t o t h e s a m e v a l u e ( 0 0 b or 11b). dinc (bit 1 3 ) d e s t i n a t i o n i n c r e m e n t , w h e n s e t t o 1 , a u t o m a t i c a l l y i n c r e m e n t s t h e d e s t i n a t i o n address after each transfer. the address is in crem ented by 1 o r 2, depending on the by te/word b it ( b n / w , bit 0). the address does not change if the in c r e m e n t a n d d e c r e m e n t b i t s a r e s e t t o t h e s a m e value (00b or 11b). s m / i o n ( b i t 1 2 ) ?source address space select selects m e m or y o r i/ o s p a c e fo r t h e s o u rc e a d d r e s s . w h e n sm/ion i s s e t t o 1 , t h e s o u rc e a d d re s s i s i n m e m o ry s p a c e , w h i l e w h e n 0 , t h e s o u rc e a d d r e s s i s in i/o space. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 s d e c ( b i t 1 1 ) s o u r c e d e c r e m e n t , w h e n s e t t o 1 , a u t o m a t i c a l l y d e c r e m e n t s t h e d e s t i n a t i o n a d d r e s s a ft e r e a c h t ra n s fe r. t h e a d d r e s s i s d e c r e m e n t e d b y 1 o r 2 , d e p e n d i n g o n t h e b y t e / w o r d b i t ( bn/w , b i t 0 ). t h e a d d re s s d o e s n o t c h a n g e i f t h e i n c re m e n t a n d d e c re m e n t b i t s a re s e t t o t h e s a m e v a l u e (0 0 b o r 11b). sinc (bit 10) s o u r c e i n c r e m e n t , w h e n s e t t o 1 , a u t o m a t i c a l l y i n c r e m e n t s t h e d e s t i n a t i o n a d d r e s s a ft e r e a c h t ra n s fe r. t h e a d d r e s s i s i n c r e m e n t e d b y 1 o r 2 , d e p e n d i n g o n t h e b y t e / w o r d b i t ( bn/w , b i t 0 ). t h e a d d re s s d o e s n o t c h a n g e i f t h e i n c re m e n t a n d d e c re m e n t b i t s a re s e t t o t h e s a m e v a l u e (0 0 b o r 11b). t c ( b i t 9 ) t e rm i n a l co u n t . the dma decrem ents the transfer count for each dma transfer. w he n t c is set to 1, the source or destination synchroni zed dma transfers terminate when the count reaches 0, but when t c is set to 0, source or destination synchr onized dma transfers do not term inate when the count reaches 0. unsynchronized dma tran sfers always end when the count reaches 0, i r r e s p e c t i v e o f t h e s e t t i n g o f t h i s b i t . i n t ( b i t 8 ) in t e rru p t . t h e d m a c h a n n e l g e n e ra t e s a n i n terrupt request on com pletion of the transfer count when this bit is set to 1. however, for an interrupt to be generated, the t c bit must also be set to 1. syn1-syn0 (bits 7-6) ? synchronization type bits select channel synchr onization as shown in the following table. the value of these bits is ignored if t d r q ( bit 4) is set to 1. a processor reset causes these bits to be set to 11b. s y n 1 s y n 0 sync type 0 0 unsynchronized 0 1 source synchronized 1 0 destination synchronized 1 1 reserved p ( b i t 5 ) ?relative priority. selects hi g h p r i o r i t y f o r t h i s c h a n n e l r e l a tive to the other channel during s i m u l t a n e o u s t ra n s fe rs w h e n s e t t o 1 . t d r q ( b i t 4 ) - tim e r 2 synchronization. enables dma reque sts from tim er 2, when set to 1, but disables dma requests f r om ti m e r 2 when set to 0. ext (bit 3 ) ? reserved. c h g ( b i t 2 ) ch a n g e s t a rt bi t . t h i s b i t m u s t b e set to 1, to allow m odifi cation of the st bit during a write. during a write, when c h g i s s e t t o 0 , st is not changed when writing the control word. t he result of reading this bit is always 0. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 s t ( b i t 1 ) ? start/stop d ma channel. w hen the start bit is set to 1, the dma channel is started. the c h g bit m u st be set to 1 for this bit to be m odifie d and only during the sam e register write. a p r o c e s s o r r e s e t c a u s e s t h i s b i t t o b e s e t t o 0 . b n / w ( b i t 0 ) b y t e / w o r d s e l e c t . w h e n s e t t o 1 , w o r d transfers are selected. w h en set to 0, byte t r a n s f e r s a r e s e l e c t e d . ( t h e i a 188em does not support word transfer s and furthermore they are not supported if the chip selects are programmed for 8-bit transfers.) d 1 t c ( 0 d 8 h ) - d m a t ransfer c oun t registers. d0tc (0c8 h) the dma transfer count reg i sters are m a intained by each dma channel. they are d ecrem ented after each dma cycle. the s t ate of the t c b i t i n t h e d m a c o n t r o l r e g i s t e r has no influence on this activity. but, if unsynchronized transfers are programm e d or if the t c b i t i n t h e d m a c o n t ro l w o rd i s s e t , d m a a c t i v i t y c e a s e s w h e n t h e t r a n s f e r c o u n t r e g i s t e r r e a c h e s 0 . the d0tc a nd d1tc registers are undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 ?tc0 tc [15:0 ] ( bits 15-0) ? dma transfer count contains the transfer count for the respective dma c h a n n e l . i t s v a l u e i s d e c r e m e n t e d a f t e r e a c h t r a n s f e r . d 1 d s t h ( 0 d 6 h ) - t h e d m a d e st i n a t i o n address h igh register. d 0 d s t h ( 0 c 6 h ) the 20-bit destination address consis ts of these four bits com b ined w i t h t h e 1 6 - b i t s o f t h e r e s p e c t i v e destination address low register. a dma transfer requires that two co mplete 16-bit registers (high and low registers) be used for both the source and des tination addresses of each dma channel involved. these four registers m ust be initial ized. each address m a y be increm ented or decrem ented independently o f t h e o t h e r a f t e r e a c h t r a n sfer. the addresses are increm ented or decrem ented by two for word transfers and increm e nted or decrem ented by 1 for byte transfers. the d0dsth and d1dsth registers are und efined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dda19-dda16 reserved [15:4 ] (bits 15-4) ? reserved. dda [19:16] ( bits 3-0) ?dma destination address high bits are driven onto a19-a16 during the write phase of a dma transfer. didst l (0d4h) - d m a d e st i n a t i o n address l ow register. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 d0dst l (0c4h) t h e s i x t e e n b i t s o f t h e s e r e g i s t e r s a r e c o m b i n e d w i t h t h e f o u r b i t s o f t h e r e s p e c t i v e d m a d e s t i n a t i o n address high register to produ c e a 2 0 - b i t d e s t i n a t i o n a d d r e s s . the d0dstl and d1dstl regist e rs a re u n d e fi n e d a t re s e t . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dda15 ?dda0 dda [15:0 ] (bits 15-0) ? dma des tination address low bits are driven onto a15-a0 during the write phase of a dma transfer. d1srch (0d2h) - d m a s ou r c e a d d r e s s h i g h register. d0srch (0c2h) t h e 2 0 - b i t s o u r c e a d d r e s s c o n s i s t s o f t h e s e f o u r b i t s c o m b i n e d w i t h t h e 1 6 - b i t s o f t h e r e s p e c t i v e s o u r c e address low register. a dma tran s f e r r e q u i r e s t h a t t w o c o m p l e t e 16-bit registers in the peripheral control block (high and low register s) be used for both the source and destination addresses of each dma channel involved. each dma channel requires that a ll four address registers be i n i t i a l i z e d . e a c h a d d r e s s m a y b e i n c r e m e n t e d o r d e c r e m e n t e d i n d e p e n d e n t l y o f t h e o t h e r a f t e r e a c h t r a n s f e r . t h e a d d r e s s e s a r e increm ented or decrem e nted by 2 for word transfers and increm ented or decrem ented by 1 for byte t r a n s f e r s . the d0srch and d1srchl registers are und efined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved dsa19 ?sa16 reserved [15:4 ] (bits 15-4) ? reserved dsa [19:16] ( bits 3-0) ? dma source address high bits are dr iven onto a19-a16 during the read phase of a dma transfer. d1srcl (0d0h) - d m a s ou r c e a d d r e s s l ow register. d0srcl (0c0h) t h e s i x t e e n b i t s o f t h e s e r e g i s t e r s a r e c o m b i n e d w i t h the four bits of the re spective dma source address high register to produce a 20-bit source address. the d0srcl and d1srcl regist ers are undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dsa15-dsa 0 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 dsa [15:0 ] (bits 15-0) ?dma source address low bits are placed on to a15-a0 during the read phase of a dma transfer. mpcs (0a8h) - mcs a n d p c s a u x i l i a r y register. this register controls m o re than one type of chip select, m a king it different fr o m t h e o t h e r c h i p s e l e c t control registers. the mpcs register contains inform ation for the following, m c s 3 _ n - m c s 0 _ n a s w e l l a s pcs6_n - pcs5_n and pcs3_n - pcs0_n . the mpcs register also contai ns a bit that configures the pcs6_n - pcs5_n pins as either chip selects or as alternate sou r ces for th e a2 and a1 address bits. either address bits a1 & a2 o r pcs6_n - pcs5_n a r e selected to the exclusion of the other. w hen progr amm e d for address bits, these outputs can be used to p ro v i d e l a t c h e d a d d re s s b i t s fo r a2 & a1 pcs6_n - pcs5_n are high and not active on processor reset. a n a c c e s s t o t h e m p c s r e g i s t e r c a u s e s t h e pins to activate, when the pcs6_n - pcs5_n are configured as address pins. the pcs6_n - pcs5_n pins do n o t r e q u i r e c o r r e s p o n d i n g a c c e s s t o t h e p a c s r e g i s t e r t o b e a c t i v a t e d . the value of the mpcs register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 m6-m0 ex ms 1 1 1 r2 r1-r0 reserved (bit 15) s e t t o 1 . m [6:0 ] (bits14-8) mcs_n block size ?these seven bits determ ine t h e t o t a l b l o c k s i z e f o r t h e mcs3_n - mcs0_n chip selects. t he total block size is divided equally am ong the four chip selects. the following table shows the relationship betw een m [ 6 : 0 ] a n d t h e s i z e o f t h e m e m o ry b l o c k . total block size individual select size m6 ? m0 8 k 2 k 0 0 0 0 0 0 1 b 1 6 k 4 k 0 0 0 0 0 1 0 b 3 2 k 8 k 0 0 0 0 1 0 0 b 6 4 k 1 6 k 0 0 0 1 0 0 0 b 1 2 8 k 3 2 k 0 0 1 0 0 0 0 b 2 5 6 k 6 4 k 0 1 0 0 0 0 0 b 5 1 2 k 1 2 8 k 1 0 0 0 0 0 0 b e x (b i t 7 ) p i n s e l e c t o r t h i s b i t d e t e r m i n e s w h e t h e r t h e pcs6_n - pcs5_n pins are configured as chip selects or as alternate outputs for a2 & a1 . w he n this bit is set to 1, pcs6_n - pcs5_n are configured as peripheral chip select pins, whereas when set to 0, pcs6_n - pcs5_n b e c o m e a d d r e s s b i t a1 and a d d r e s s b i t a 2 respectively. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 ms (bit 6) memory/ i/o space selector d e t e r m i n e s w h e t h e r t h e pcs_n pins are active either during m e mory or i/o bus cycles. w hen m s i s s e t t o 1 , t h e pcs_n outputs are active for m e m o ry bus cycles, and active for i/o bus cycles when set to 0. reserved (bits 5:3) s e t t o 1 . r 2 ( b i t 2 ) r e a d y m o d e ? this bit influences only the pcs6_n - pcs5_n chip selects. if r 2 i s s e t t o 0 , e x t e r n a l r e a d y i s required. if r 2 is set to 1, external re ady is ignored. in each case, the values of the r1-r0 b i t s d e t e r m i n e t h e n u m b e r o f w a i t s t a t e s t o b e i n s e r t e d . r [ 1 : 0 ] (bits 1-0) wait-state value these bits influence only the pcs6_n - pcs5_n chip selects. t he value of r 1 - r 0 d e t e rm i n e s t h e n u m b e r o f w a i t s t a t e s i n s e rt ed into an access depending on whether its to the pcs_n m e m ory or i/o area. up t o t h r e e w a i t s t a t e s c a n b e i n s e r t e d ( r1 - r0 = 0 0 b t o 1 1 b ) . mmcs (0a6h) - m i d r a n g e m e m o r y c h i p s elect register. four chip-select pins, mcs3_n - mcs0_n , a r e p r o v i d e d f o r u s e w i t h i n a u s e r - l o c a t a b l e m e m o r y b l o c k . t h e m e mory block base address can be located anywhe re within the 1-mbyte m e mory address space, e x c l u d i n g t h e a r e a s a s s o c i a t e d w i t h t h e ucs_n and l c s _ n chip selects (and, if m a p p e d t o m e m o r y , t h e address range of the pe ri p h e ra l ch i p s e l e c t s , pcs6_n - pcs5_n and pcs3_n to pcs0_n ). if t h e p c s _ n c h i p selects are m a pped to i/o space, the m c s _ n address range can overlap the pcs_n address range two registers program the midrange chip selects. the midrange mem o r y chip select (mmcs) register determ ines the base address, the ready condition and wait states of the m e mory block that are accessed through the m c s _ n pins. the pcs_n and mcs_n a u x i l i a ry ( m p cs ) re g i s t e r c o n f i g u r e s t h e b l o c k s i z e . o n r e s e t t h e mcs3_n - m c s 0 _ n p i n s a r e n o t a c t i v e . a c c e s s i n g w i t h a write both the mmcs and mpcs r e g i s t e r s a c t i v a t e s t h e s e c h i p s e l e c t s . the m c s 3 _ n - m c s 0 _ n o u t p u t s a s s e r t w i t h t h e m u l t i p l e x e d a d a d d r e s s b u s ( ad15 ?ad0 o r ao15 ?ao8 and ad7 ?ad0 ) r a t h e r t h a n t h e e a r l i e r t i m i n g o f t h e a19 ?a0 b u s u n l i k e t h e ucs_n and l c s _ n c h i p s e l e c t s . the tim ing is delayed for a half cycle later than that for u c s _ n and l c s _ n i f t h e a19 ? a0 bus is used for address selection. t h e v a l u e o f t h e m m cs re g i s t e r is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ba19 ?ba13 1 1 1 1 1 1 r2 r1 - r0 ba [15:9 ] ( bits 15-9) ? base address. the value of the ba19 ? ba13 determ ines the base address of t h e m e m o ry b l o c k t h a t i s a d d re s s e d b y t h e m c s _ n chip select pins. thes e bits correspond to bits a 1 9 a13 o f t h e 2 0 - b i t m e m o r y a d d r e s s . t h e r e m a i n i n g b i t s a12 ? a0 of the base address are always 0. t h e b a s e a d d r e s s m a y b e a n y i n t e g e r m u l t i p l e o f t h e s i z e o f t h e m e m o r y c l o c k s e l e c t e d i n t h e m p c s register. for exam ple, if the m i drange block is 32 kbytes, the block c ould be located at 20000h or 28000h but not at 24000h. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 if t h e l c s _ n chip select is inactive, the base address of the m i drange ch ip selects can be set to 00000h, b e c a u s e t h e l c s _ n chip select is defined to be 00000h but is unused. the furthe r l i m i t a t i o n t h a t t h e base address m ust be an integer m ultiple of the block size m eans that a 512k mmcs block size can only be used with the l c s _ n chip select inactive and the base addr ess of the m i drange c h i p s e l e c t s s e t to 00000h. reserved [8:3 ] (bits 8-3 ) - s e t t o 1 . r2 (bit 2) ? ready m ode . this bit determ ines the m c s _ n chip selects ready m ode. when r 2 i s 0 , a n external ready is necessary. if r 2 is 1, an external rea dy is ignored. in each c a s e , t h e n u m b e r o f w a i t states ins e rted in an access is determ ined by the value of th e r1 & r0 b i t s . r [ 1 : 0 ] ( b i t s 1 - 0 ) ? wait-state value. the num ber of wait stat e s i n s e r t e d i n a n a c c e s s i s d e t e r m i n e d by the value of the r1 & r0 bits. up to three wait states can be inserted ( r1 - r0 = 00b to 11b). pacs (0a4h) - p e r i p h e r a l c h i p s elec t r e g i s t e r . the peripheral chip selects are as se rted over 256-byte range with the sa m e ti m i ng as the ad address bus. there are six chip selects, pcs6_n - pcs5_n and pcs3_n - pcs0_n , t h a t a r e u t i l i z e d i n e i t h e r t h e u s e r - locatable m e mory or i/o blocks. the pcs4_n c h i p s e l e c t i s n o t i m p l e m e n t e d i n t h e i a 1 8 x e m f a m i l y o f micro con t rollers. exclu ding the areas utilized b y the ucs_n, lcs_n, and m c s _ n c h i p s e l e c t s , t h e m e m o r y block can be located any w here within the 1-mby t e a d d r e s s s p a c e . t h e s e c h i p selects m a y also be configured to access the 64-kbyte i/o space. programm i ng the periph eral chip sel e c t s u s e s t w o r e g i s t e r s , t h e p e r i p h e ra l ch i p s e l e c t (p a cs ) re g i s t e r a n d t h e p c s _ n and m c s _ n a u x i l i a r y ( m p c s ) r e g i s t e r . t h e p a c s r e g i s t e r e s t a b l i s h e s t h e b a s e a d d r e s s , configures the ready m ode, and determ ines the num ber of wa it states for the pcs3_n - pcs0_n o u t p u t s . the mpcs register configures the pcs6_n ?pcs5_n pins to be either chip selects or address pins a1 and a2 . w hen these pins are configured a s c h i p s e l e c t s , t h e m p c s r e g i s t e r d e t e r m i n e s w h e t h e r t h e y a r e a c t i v e during m e mory or i/o bus cycles and determ ines the ready s t ate and wait states for these output pins. these pins are not active on reset but are activated as chip selects by writing to the two registers (pacs and mpcs). to configure and activate them as address p i n s i t i s n e c e s s a r y t o w r i t e t o b o t h t h e p a c s a n d mpcs registers. pcs6_n ?pcs5_n can be configured for 0 to 3 wait states while pcs3_n - pcs0_n c a n b e p r o g r a m m e d f o r 0 t o 1 5 w a i t s t a t e s . the value of the pacs register is undefined at reset. 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 ba19 ?ba1 1 1 1 1 r3 r2 r1 ?0 ba [19:11 ] (bits 15-7) - base address bits determine the base address and correspond to bits 19 - 11 of the 20-bit programm a ble base address of the peri pheral chip select block. however, if the pcs_n c h i p s e l e c t s a re m a p p e d t o i/ o s p a c e, these bits m ust be set to 0000b, a s i / o a d d r e s s e s a r e o n l y 1 6 b i t s wide. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 pcs address ranges range p c s n l i n e l o w h i g h pcs0n base address base address + 255 pcs1n base address + 256 base address + 511 pcs2n base address + 512 base address + 767 pcs3n base address + 768 base address + 1023 reserved n/a n/a pcs5n base address + 1280 base address pcs6n base address + 1536 base address reserved [6:4 ] (bits 6-4 ) s e t t o 1 . r [3 ] (bit 3) ? w a it state value. see the following table. r [ 2 ] ( b i t 2 ) ?ready mode. w hen 0, external ready is re q u i re d . w h e n 1 , e x t e rn al ready is ignored. b u t i n e a c h c a s e t h e n u m b e r o f w a i t s t a t e s is d e term ined as in the following table. r [ 1 : 0 ] ( b i t s 1 0 ) ? w a it-state value. s ee following table. it should be noted that p c s6_n ?pcs5_n and pcs3_n ?pcs0_n pins are m ultiplexed with the programm a ble i/o pins. and for them to funct i on as chip selects, the pio mode and direction setti n g s fo r t h e s e p i n s m u s t b e s e t t o 0 fo r n o rm a l operation. pcs3n ?p c s0n wait?tate encoding r 3 r 1 r 0 wait states 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 5 1 0 1 7 1 1 0 9 1 1 1 15 lmcs (0a2h) - low memory chip select register configures the low me m o r y c h i p s e l e c t t h a t h a s been provided to facilitate access to the interrupt vector table located a t 0 0 0 0 0 h o r t h e b o t t o m o f m e m o ry . the l c s _ n pin is not active at reset. the width of the data bus for the l c s _ n s p a c e s h o u l d b e c o n f i g u r e d i n the auxcon register before a c t i v a t i n g t h e l c s _ n c h i p s e l e c t p i n , b y a n y w r i t e access to the lmcs register. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 the value of the lmcs register is undefined at reset except d a , which is set to 0. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ub2 ? ub0 1 1 1 1 da pse 1 1 1 r2 r1-r0 reserved [15 ] (bit 15) s e t t o 0 ub [2:0 ] (bits 14 ? 12) - upper boundary . these bits define the upper boundary of mem ory accessed b y t h e l c s _ n c h i p s e l e c t . t h e f o l l o w i n g t a b l e g i v e s t h e possible configurations of block size (m ax 512kbytes). lmc s bl o c k s i z e p r o g r a m m i n g v a l u e s m e m o r y b l o c k s i z e e n d i n g address u b 2 u b 0 64k 0ffffh 000b 128k 1ffffh 001b 256k 3ffffh 011b 512k 7ffffh 111b reserved [11:8 ] (bits 11-8) - s e t t o 1 . d a (b i t 7 ) d i s a b l e a d d r e s s - w hen set to 0, the address is driven onto the address bus ( ad15 ?ad0 ) during the address phase of a bus cycle. if d a is set to 1, the address bus is disabled, providing som e m e a s u re o f p o w e r s a v i n g . t h i s b i t i s s e t t o 0 a t r e s e t . if bhe_n/aden_n is held at 0 during the rising edge of r e s _ n , then the address bus is always driven, independent of the setting of d a . p s e ( b i t 6 ) p s r a m m o d e e n a b l e p s ra m s u p p o rt fo r t h e lcs_n c h i p s e l e c t m e m o r y s p a c e i s e n a b l e d when the pse is set to 1. the edram, mdram, and cdram refresh control unit registers must be configured for auto refresh before psram s u p p o r t i s e n a b l e d . s e t t i n g t h e e n a b l e b i t ( e n ) i n t h e enable rcu regis t er (e dram, offs et e4h) configures the mcs3_n/rfsh_n a s r fs h _ n . reserved (bits 5-3) ? s e t t o 1 . r 2 (b i t 2 ) - r e a d y m o d e . w h e n t h i s b i t i s s e t t o 0 , a n e x t e r n a l re a d y i s re q u i re d . w h e n s e t t o 1 , t h e external ready is ignored. in eith er case, however, the value of the r 1 - r 0 bits determ ine the number of wait states inserted. r [ 1 : 0 ] ( b i t s r 1 - r 0 ) - w a i t - s t a t e v a l u e . t h e n u m b e r o f w a i t s t a t e s i n s e r t e d i n t o a n a c c e s s t o t h e lcs_n m e mory area is determ ined by the value of these bits. this num ber ranges from 0 to 3 ( r1 ?r0 = 00b to 11b) umcs (0a0h) - u pper m e m o r y c h i p s elect register configures the upper mem ory chip select pin, which is used for the top of m e m ory. on reset, th e first fetch takes place at m e m ory location fff f0h and thus this area of m e m ory is usually used for instruc tion m e mory. w ith this in m i nd, ucs_n defa ults to an 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 active state at reset with a m e mo ry range of 64 kbytes (f0000h to fffffh), external ready required, and t h re e w a i t s t a t e s a u t o m a t i c a l l y i n serted. the upper end of the m e m ory range always ends at fffffh, whereas the lower end of this uppe r m e mory range is programmable. the value of the umcs register is f 03bh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 lb2 ? lb0 0 0 0 0 da 0 1 1 1 r2 r1-r0 reserved [15 ] (bit 15) s e t t o 1 . lb [2:0 ] (bits 14?2) ? lower boundary. these bits determ ine the botto m of the m e mory access e d b y t h e u c s _ n chip selects. u mc s bl o c k s i z e p r o g r a m m i n g v a l u e s m e m o r y block s i z e s t a r t i n g address l b 2 l b 0 c o m m e n t s 64k f0000h 111b default 128k e0000h 110b 256k c0000h 100b 512k 80000h 000b reserved (bits 11 ?8) d a (b i t 7 ) d i s a b l e a d d r e s s . w h e n s e t t o 0 , t h e a d d r e s s i s driven onto the address bus ( ad15 ?ad0 ) during the address phase of a bus cycle when u c s _ n is asserted. if d a is set to 1, the address bus is disabled, and the address is not driven on the address bus w hen ucs_n is asserted, providing som e m e a s u re o f p o w e r s a v i n g . t h i s b i t i s s e t t o 0 a t r e s e t . if bhe_n/aden_n is held at 0 during the rising edge of r e s _ n , then the address bus is always driven independent of the setting of d a . reserved (bit 6) ? s e t t o 0 . reserved (bit 5 ?3) ?set to 1 . r 2 ( b i t 2 ) r e a d y m o d e w h e n t h i s b i t i s s e t t o 0 , a n e x t e rn a l re a d y i s re q u i r e d . b u t w h e n s e t t o 1 , t h e external ready is ignored. in eith er case, however, the value of the r1 - r0 bits determ ine the number of wait states inserted. r [1:0 ] (bits 1-0) - wait-state value . t h e n u m b e r o f w a i t s t a t e s i n s e r t e d i n t o a n a c c e s s t o t h e l c s _ n m e mory area is determ ined by the value of these bits. this num ber ranges from 0 to 3 ( r1 ?r0 = 00b t o 1 1 b ). spbaud (088h) - s erial p o r t baud rate divisor register. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 t h e v a l u e i n t h i s re g i s t e r d e t e rm i n e s t h e n u m b e r o f i n ternal processor cycles in one phase (half-period) of the 32 x serial clock. the contents of these registers m ust be adjusted to reflect the new processor clock frequency if power- save m ode is in effect. t h e b a u d r a t e d i v i s o r m a y b e c a l c u l a t e d f r o m : bauddiv = (processor frequenc y / (32 x baud rate)) -1 by setting the bauddiv to 0000h, the m a xi m u m baud rate of 1/32 of the intern al processor frequency clock is set. setting ba uddiv to 1 29 (81h) provides a baud rate of 9600 at 40mhz. the baud rate tolerance is +4.6% and ?.9% with respect to the actual serial port ba ud rate, not the target baud rate. baud rates divisor b ased on cpu clock rate b aud rate 2 0 m h z 2 5 m h z 3 3 m h z 4 0 m h z 300 2082 2603 3471 4165 600 1040 1301 1735 2082 1200 519 650 867 1040 2400 259 324 433 519 4800 129 161 216 259 9600 64 80 107 129 14400 42 53 71 85 19200 31 39 53 64 625 kbaud 0 n/a n/a 1 7 8 1 . 2 5 k b a u d n / a 0 n / a n / a 1 . 0 4 1 m b a u d n / a n / a 0 n / a 1 . 2 5 m b a u d n / a n / a n / a 0 the value of the spbaud regist er at reset is undefined. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bauddiv bauddiv [15:0 ] (bits 15-0) ? baud rate divisor . defines the divisor for the internal processor c l o c k . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 s p r d ( 0 8 6 h ) - s erial p o r t r e c e i v e d a t a r e g i s t e r . d a t a r e c e i v e d o v e r t h e s e r i a l p o r t a r e s t o r e d i n t h i s r e g i s t e r u n t i l r e a d . t h e d a t a a r e r e c e i v e d i n i t i a l l y b y t h e r e c e i v e s h i f t r e g i s t e r ( n o s o f t w a r e a c c e s s ) p e r m i t t i n g d a t a t o b e r e c e i v e d w h i l e t h e p r e v i o u s d a t a a r e being read. the r d r b i t ( r e c e i v e d a t a r e a d y ) i n t h e s e r i a l p o r t s t a t u s re g i s t e r i n d i c a t e s the status of the sprd register. setting the r d r b i t 1 i n d i c a t e s t h a t t h e r e i s v a l i d data in the receive reg i ster. the value of the sprd register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved rdata reserved (bits 15-8) ? r e s e r v e d . rdata [7:0 ] ( bits 7-0) h o l d s v a l i d d a t a w h i l e t h e r d r b i t o f t h e s t a t u s r e g i s t e r i s s e t . sptd (084h) - s erial p o r t t ransm i t d a t a r e g i s t e r . data is written to this register by s o f t w a r e , w i t h t h e v a l u e s t o b e t r ansm itted by the serial port. double buffering of the transm itter allows for the transm i s s i o n o f d a t a f r o m t h e t r a n s m i t s h i f t r e g i s t e r ( n o software access), while the next data ar e w r i t t e n i n t o t h e t r a n s m i t r e g i s t e r . the t h r e b i t i n t h e s e r i a l p o r t s t a t u s r e g i s t e r i n d i c a t e s w h e t h e r t h e re i s valid data in the spdt register. the t h r e b i t m u s t b e a 1 b e fo re w ri t i n g d a t a t o t h i s re gister to prevent overwrit i n g v a l i d d a t a t h a t i s already in the spdt register. the value of the sptd register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tdata reserved (bits 15-8) ? r e s e r v e d . tdata [7:0 ] ( bits 7-0) h o l d s t h e d a t a t o b e t r a n s m i t t e d . s p s t s ( 0 8 2 h ) ? s erial p o r t st a t u s r e g i s t e r. this register stores inform ation c oncerning the current status of the por t. the status bits are described below. the value of the spsts register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved temt thre rdr brki fer per oer 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 reserved (bits 15-7) ? reserved ?set to 0 . temt ( bit 6) ?transmitter empty . w h e n b o t h t h e t r a n s m i t s h i f t r e g i s t e r a n d t h e t r a n s m i t r e g i s t e r a r e e m p t y , t h i s b i t i s s e t i n d i c a t i n g t o s o f t w a r e t h a t i t i s s a f e t o d i s a b l e t h e t r a n s m i t t e r . t h i s b i t i s re a d -o n l y . thre (bit 5) ? transmit holding register empty. w h e n t h i s b i t i s 1 , t h e c o r r e s p o n d i n g t r a n s m i t h o l d i n g r e g i s t e r i s r e a d y t o a c c e p t d a t a . t h i s i s a re a d -o n l y b i t . r d r ( b i t 4 ) r e c e i v e d a t a r e a d y . w h e n t h i s b i t i s 1 , t h e r e s p e c tive sprd register contains valid d a t a . t h i s i s a r e a d / w r i t e b i t a n d c a n b e r e s e t only by reading the correspo nding receive regis t er. brki (bit 3 ) break interrupt. t h i s b i t i n d i c a t e s t h a t a b r e a k h a s b e e n r e c e i v e d w h e n t h i s b i t i s s e t t o 1 a n d c a u s e s a s e r i a l p o rt interrupt request. n o t e : this bit should be reset by software. fer (bit 2 ) ? framing error detected . w h e n t h e r e c e i v e r s a m p l e s t h e r x d l i n e a s l o w w h e n a s t o p b i t is expected (line high) a fra m ing e r r o r i s g e n e r a t e d s e t t i n g t h i s b i t . n o t e : this bit should be reset by software. per (bit 1 ) - parity error detected . w h e n a p a r i t y e r r o r i s d e t e c t e d i n either m ode 1 or 3, this bit is s e t . n o t e : this bit should be reset by software. oer (bit 0) ? overrun error detected . w h e n n e w d a t a o v e rw ri t e s v a l i d d a t a i n t h e r e c e i v e r e g i s t e r (becaus e it h a sn? been read) an overrun error is d e tected setting this bit. n o t e : this bit should be reset by software. spct (080h) - s erial p o r t control register. this register controls both transm it a nd receive parts of the serial port. the value of the spct register is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tx i e rx i e l o o p b r k b r k val pmode wlgn stp tmode rsie rmode reserved (bits 15-12) ? r e s e r v e d . s e t t o 0 . t x i e ( b i t 1 1 ) t r a n s m i t t e r r e a d y i n t e r r u p t e n a b l e . this b i t enables the ge neration of an interrupt re q u e s t s w h e n e v e r t h e t ra n s m i t holding register is em pty ( thre b i t 1 ) . t h e r e s p e c t i v e p o r t d o e s n o t generate interrupts when this bit is 0. interrupts continue to be generated as long as t h r e a n d t h e t x ie a r e 1 . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 rxie (bit 10) ? receive data ready interrup t en able . t h i s b i t e n a b l e s t h e g e n e r a t i o n o f a n i n t e r r u p t r e q u e s t s w h e n e v e r t h e r e c e i v e r e gister contains v a lid data ( r d r b i t 1 ) . t h e r e s p e c t i v e p o r t d o e s n o t generate interrupts when this bit is 0. interrupts continue to be generated as long as r d r a n d t h e rxie a r e 1 . loop (bit 9) ? loop-back . the serial port is placed into the loop- back m ode when this bit is set. b r k ( b i t 8 ) s e n d b r e a k . w hen this bit is set to 1, the t x d pin is driven low, overriding any data that m a y be in the course of being shifte d out of the transm it shift register. see the definitions of long and short break in the serial port status register definition. brkval (bit 7) ? b r e a k v a l u e . t h i s i s t h e n i n t h d a t a b i t t r a n s m i t t e d w h e n i n m o d e s 2 a n d 3 . t h i s b i t is cleared at each transm itted word an d is not buffe r e d . t o t r a n s m i t d a t a w i t h t h i s b i t s e t h i g h , t h e following procedure is recommended. 1. the temt bit in the serial port status register m ust go high. 2. s e t t h e t b 8 b i t b y w r i t i n g i t t o t h e s e r i a l p o r t c o n t r o l r e g i s t e r . 3. f i n a l l y w r i t e t h e t r a n s m i t c h a r a c t e r t o t h e s e r i a l p o r t t r a n s m i t r e g i s t e r . s e r i a l p o r t 0 i s a s p e c i a l c a s e i n t h a t i f t h i s b i t i s 1, the associated pins a r e u s e d f o r f l o w c o n t r o l overriding the peripheral chip select si gnals. t his bit is 0 at reset. pmode (bi t s6:5) ?parity mode . w h e n t h i s b i t i s s e t t o 1 , t h e t x d pin is driven low overriding any data that m a y be in the cour se of being shifted out of t h e t r a n s m i t s h i f t r e g i s t e r . see the definitions of long and short break in the serial port status register definition. w l g n ( b i t 4 ) w o r d l e n g t h . t h e n u m b e r o f b i t s t r a n s m i t t e d o r re c e i v e d i n a fra m e i s d e t e rm i n e d b y t h e v a l u e o f t h i s b i t . w h e n t h i s b i t i s 0 , t h e n u m b e r o f d a t a b i t s i n a f r a m e i s 7 w h e r e a s w h e n t h i s b i t i s 1 the num be r of data bits in a fram e is 8. this bit is 0 at reset. s t p ( b i t 3 ) s t o p b i t s . t h i s b i t s p e c i f i e s t h e n u m b er of stop bits used to indi cate th e end of a fram e. when this bit is 0, the number of stop bits is 1. when it is 1, the num ber of stop bits is 2. this bit is 0 a t r e s e t . t m o d e (b i t 2 ) t r a n s m i t m o d e . t h e t ra n s m i t s e c t i o n o f t h e s e ri a l port is enabled when this bit is 1 and disabled when this bit is 0. r s i e ( b i t 1 ) r e c e i v e s t a t u s i n t e r r u p t e n a b l e . wh e n a n e x c e p t i o n o c c u rs d u ri n g d a t a re c e p t i o n a n i n t e r r u p t r e q u e s t i s g e n e r a t e d i f e n a b l e d b y t h i s b i t ( r s i e = 1). interrupt requests are made for the e rro r c o n d i t i o n s l i s t e d ( b r k , o e r , p e r , a n d f e r ) i n t h e s e r i a l p o r t s t a t u s re g i s t e r. t h i s b i t i s 0 a t r e s e t . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 rmode (bi t 0) ?receive mode . the receive section of the serial por t is enabled when this bit is 1 and disabled when this bit is 0. t h i s b i t i s 0 a t re s e t . pdata1 (07ah) - p i o d a t a r e g i s t e r s . pdata0 (074h), when a pio pin is configured as an output the value in the corresponding pio data register bit is driven onto the pin. on the other hand, if the pio pin is conf i g u re d a s a n i n p u t , t h e v a l u e o n t h e p i n i s i n p u t i n t o the corresponding bit of the pio data register. t h e f o l l o w i n g t a b l e l i s t s t h e d e f a u l t s t a t e s f o r t h e p i o p i n s . p i o p i n a s s i g n m e n ts p i o number associated pin name p o w e r - o n r e s e t status 0 t m r i n 1 i n p u t w i t h p u l l - u p 1 t m r o u t 1 i n p u t w i t h p u l l - d o w n 2 p c s 6 / a 2 i n p u t w i t h p u l l - u p 3 p c s 5 / a 1 i n p u t w i t h p u l l - u p 4 d t / r _ n n o r m a l o p e r a t i o n (c) 5 d e n _ n / d s _ n n o r m a l o p e r a t i o n ( c ) 6 s r d y n o r m a l o p e r a t i o n (d) 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p i o number associated pin name p o w e r - o n r e s e t status 7 (a) a 1 7 n o r m a l o p e r a t i o n ( c ) 8 (a) a 1 8 n o r m a l o p e r a t i o n ( c ) 9 (a) a 1 9 n o r m a l o p e r a t i o n ( c ) 1 0 t m r o u t 0 i n p u t w i t h p u l l - d o w n 1 1 t m r i n 0 i n p u t w i t h p u l l - u p 1 2 d r q 0 i n p u t w i t h p u l l - u p 1 3 d r q 1 i n p u t w i t h p u l l - u p 1 4 m c s 0 _ n i n p u t w i t h p u l l - u p 1 5 m c s 1 _ n i n p u t w i t h p u l l - u p 1 6 p c s 0 _ n i n p u t w i t h p u l l - u p 1 7 p c s 1 _ n i n p u t w i t h p u l l - u p 1 8 p c s 2 _ n i n p u t w i t h p u l l - u p 1 9 p c s 3 _ n i n p u t w i t h p u l l - u p 2 0 s c l k i n p u t w i t h p u l l - u p 2 1 s d a t a i n p u t w i t h p u l l - u p 2 2 s d e n 0 i n p u t w i t h p u l l - d o w n 2 3 s d e n 1 i n p u t w i t h p u l l - d o w n 2 4 m c s 2 _ n i n p u t w i t h p u l l - u p 2 5 m c s 3 _ n / r f s h _ n i n p u t w i t h p u l l - u p 2 6 (a, b) u z i i n p u t w i t h p u l l - u p 2 7 t x d i n p u t w i t h p u l l - u p 2 8 r x d i n p u t w i t h p u l l - u p 2 9 (a, b) s 6 / c l k d i v 2 _ n i n p u t w i t h p u l l - u p 3 0 i n t 4 i n p u t w i t h p u l l - u p 3 1 i n t 2 i n p u t w i t h p u l l - u p n o t e s 1. e m u l a t o r s u s e t h e s e p i n s . ( s2_n-s0_n, res_n, nmi, clkouta, bhe_n, ale, ad15 ?ad0 , and a16 ?a0 a r e used by em ulators also.) 2. if bhe_n/aden_n (ia186em) or rfsh2_n/aden (ia188em) is he ld low during power-on reset, these pins revert to norm al operation. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3. when used as a pio pin, it is an input with an available pull-up option. 4. when used as a pio pin, it is an input with an available pull-down option. the value of the pdata registers is undefined at reset. p d a t a 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p d a t a ( 1 5 0 ) p d a t a 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdata (31 ? 16) pdata [15: 0 ] (bits 15-0) ? p io d a t a 0 b i t s . t his register contains the va l u e s o f t h e b i t s t h a t a r e either driven on or received fr om the corresponding pio pins, depe nding on its configur ation each pin as either an output or an input. the values of these bits co rrespond to those in the p i o direction r e g i s t e r s a n d p i o mode registers. pdata [31: 16 ] (bits 15-0) ? p io d a t a 1 b i t s . t his register contains the va l u e s o f t h e b i t s t h a t a r e either driven on, or received from , the correspondi ng pio pins depending on its conf iguration each pin as either an output or an input. the values of these bits co rrespond to those in the p i o direction r e g i s t e r s a n d p i o mode registers the pio pins can be operate d as open-drain outputs by: 1. m a i n t a i n i n g t h e d a t a c o n s t a n t i n t h e a p p r o p r i a t e b i t o f t h e p i o d a t a r e g i s t e r . 2. w r i t i n g t h e v a l u e o f t h e d a t a b i t i n t o t h e r e s p e c t i v e b i t p o s i t i o n o f t h e p i o d i r e c t i o n r e g i s t e r , s o t h a t the output is either 0 or disabled de pending on the value of the data bit. pdir1 (078h) - p i o dir e c t i o n re g i s t e rs . pdir0 (072h) each pio pin is configured as an input or an output by the corresponding bit in th e pio direction register. pio mode and pio direction settings pio mode pio direction pin function 0 0 nor m al operation 0 1 pio input with pullup/pulldown 1 0 pio output 1 1 pio input without pullup/pulldown 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p d i r 0 the value of the pdir0 regi ster is fc0fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdir (15 ? 0) p d i r 1 the value of the pdir1 register is ffffh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pdir (31 ? 16) pdir [15:0] (bits 15-0) ? pio direction 0 bits . f o r e a c h b i t , i f t h e v a l u e is 1, th e pin is configured as an input and as an output if the value is 0. th e values of these bits co rrespond to those in the pio data registers and pi o mode registers. pdir [31:16 ] (bits 15-0) ? pio direction 1 bits . for each bit, if the value is 1, the p i n is configured as an input and as an output if the value is 0. th e values of these bits co rrespond to those in the pio data registers and pi o mode registers. piomode1 (076h) - p i o m o d e r e g i s t e r s . piomode0 (070h) each pio pin is configured as an input or an output by the corresponding bit in th e pio direction register. the bit number of pmode corresponds to the pio num ber. see the table pio mode and pio direction settings in pdir description above . piomode0 the value of the piomode0 register is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p m o d e ( 1 5 0 ) piomode1 the value of the piomode1 register is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p m o d e ( 3 1 1 6 ) 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 pmode [15:0 ] (bits 15-0) ? pio mode 0 bits . f o r e a c h b i t , i f t h e v a l u e i s 1 t h e n t h e p i n i s configured as an input and as an output if the value is 0. the values of these bits correspond to those i n t h e p i o d a t a r e g i s t e r s and pio mode registers. pmode [31:16 ] (bits 15-0) ? pio mode 1 bits . f o r e a c h b i t , i f t h e v a l u e i s 1 t h e n t h e p i n i s configured as an input and as an output if the value is 0. the values of these bits correspond to those i n t h e p i o d a t a r e g i s t e r s and pio mode registers. t1con (05eh) - t i m e r 0 and t i m e r 1 m o d e a n d c o n t r o l r e g i s t e r s . t 0con (056h) t h i s r e g i s t e r s c o n t r o l s t h e operation of the tim e r 1 and tim e r 0 respectively. the value of both the t0con and t1con registers is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en in hn in t riu 0 0 0 0 0 0 mc rtg p ext alt c on t e n ( b i t 1 5 ) e n a b l e b i t . t h e t i m e r i s e n a b l e d w h e n t h e e n b i t i s 1 . t h e t i m e r c o u n t i s i n h i b i t e d w h e n t h e e n b i t i s 0 . t h i s b i t i s w r i t e - o n l y , b u t w i t h t h e i n h n bit set to 1 in the same write operation. inhn (bit 14) ? i n h i b i t b i t . g a t e s t h e s e t t i n g o f t h e e n a b l e ( e n ) b i t . t h i s b i t m u s t b e s e t t o 1 i n t h e sam e write operation that sets the enable ( e n ) b i t . o t h e r w i s e , t h e e n b i t w i l l n o t b e c h a n g e d . t h i s b i t always reads as 0. i n t ( b i t 1 3 ) i n t e r r u p t b i t . an interrupt request is generated wh en the count reg i ster reaches its m a x i m u m , m c = 1 , b y s e t t i n g t h e i n t b i t t o 1 . in d u a l m a x c o u n t m o d e , a n i n t e rru p t re q u e s t i s generated when the count register reaches the va lue in m a xcount a or m a xcount b. no interrupt requests are generated if this bit is set to 0. if an interrupt requ e s t i s g e n e r a t e d a n d t h e n t h e e n a b l e b i t i s c l e a r e d b e f o r e s a i d i n t e r r u p t i s s e r v i c e d , t h e i n t e r r u p t r e q u e s t w i l l r e m a i n . r i u ( b i t 1 2 ) ? register in use bit . t h i s b i t i s s e t t o 1 w h e n t h e m a xcount register b is used to c o m p a r e t o t h e t i m e r c o u n t v a l u e . i t i s s e t t o 0 when the m a xcount com pare a register is used. reserved (bits 11-6) ? s e t t o 0 . mc (bit 5) ?maximum count . w h e n t h e t i m e r r e a c h e s i t s m a x i m u m c o u n t t h i s b i t i s s e t t o 1 regardless of the interrupt enable bi t. this bit is also set every t i m e m a x c o u n t c o m p a r e r e g i s t e r a o r b i s r e a c h e d , w h e n i n d u a l m a x c o u n t m o d e . t h i s b i t m a y b e u s e d b y s o f t w a r e p o l l i n g t o m o n i t o r t i m e r s t a t u s r a t h e r t h a n through interrupts if desired. r t g ( b i t 4 ) r e t r i g g e r b i t . this pin controls the tim er function o f t h e t i m e r i n p u t p i n . w h e n s e t t o 1 , t h e c o u n t i s re s e t b y a 0 to 1 transition on t i m r i n 0 o r tmrin1. w hen set to 0, a high input on t m r i n 0 o r t m r i n 1 enables the count and a 1 holds the tim e r value. t h i s b i t i s i g n o r e d if the external clocking (ext=1) bit is set. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p (b i t 3 ) p r e s c a l e r b i t . p is ignored if extern al clocking is enabled ( e x t = 1 ) . t i m e r 2 p r e s c a l e s t h e t i m e r w h e n p i s s e t t o 1 . o t h e r w i s e , t h e t i m e r is increm ented on every fourth clkout cycle. e x t ( b i t 2 ) e x t e r n a l c l o c k b i t . t h i s b i t d e t e r m i n e s w h e t h e r a n e x ternal or internal clock is used. e x t = 1, an external clock is used and e x t = 0, an internal is used. a l t ( b i t 1 ) a l t e r n a t e c o m p a r e b i t . i f s e t t o 1 , t h e t i m e r w i l l c o u n t t o m a x c o u n t c o m p a r e a , r e s e t the count register to 0, count to m a xcount com p are b, reset the count register to 0 and begin again at m a x c o u n t c o m p a r e a . i f s e t t o 0 , t h e t i m e r w i l l c o u n t t o m a x c o u n t c o m p a r e a, reset the count register to 0, and begin again a t m a x c o u n t c o m p a r e a . m a x c o u n t c o m p are b is not used in this case. cont (bit 0) ? continuous mode bit . t h e t i m e r w i l l r u n c o n t i n u o u s l y w h e n t h i s b i t i s s e t t o 1 . t h e t i m e r w i l l s t o p a f t e r e a c h c o u n t r u n a n d e n w i l l b e c l e a r e d i f t h e c o n t b i t i s s e t t o 0 . i f co nt = 1 and a l t = 1, the respective tim er counts to the maxcount compare a value and resets, then c o m m e n c e s c o u n t i n g t o m a x c o u n t c o m p a r e b value, resets and ceases co unting. t2con (066h) - t i m e r 2 m o d e and c o n t r o l r e g i s t e r . this register controls the operation of the tim e r 2. the value of the t2con register is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en inhn int 0 0 0 0 0 0 0 mc 0 0 0 0 cont e n ( b i t 1 5 ) e n a b l e b i t . t h e t i m e r i s e n a b l e d w h e n t h e e n b i t i s 1 . t h e t i m e r c o u n t i s i n h i b i t e d when the e n bit is 0. s e tting this bit to 1 by writing t o t h e t 2 c o n r e g i s t e r r e q u i r e s t h a t t h e inh b i t b e set to 1 during the sam e write. this b i t i s w r i t e - o n l y , b u t w i t h t h e i n h n b i t s e t t o 1 i n t h e s a m e w r i t e operation. inhn (bit 14) ? i n h i b i t b i t . g a t e s t h e s e t t i n g o f t h e e n a b l e ( e n ) b i t . t h i s b i t m u s t b e s e t t o 1 i n t h e sam e write operation that sets the enable ( e n ) bit. this bit always reads as 0. i n t ( b i t 1 3 ) i n t e r r u p t b i t . an interrupt request is generated, by setting the int bit to 1, when the count register reaches its m a xi m u m, m c = 1. reserved (bits 12-6) ? s e t t o 0 . m c (b i t 5 ) m a x i m u m co u n t . w h e n t h e t i m e r r e a c h e s i t s m a x i m u m c o u n t t h i s b i t i s s e t t o 1 , regardless of the interrupt enable bi t . t h i s b i t m a y b e u s e d b y s o f t w a r e p o l l i n g t o m o n i t o r t i m e r s t a t u s rather than through interrupts if desired. reserved (bits 4-1) ?set to 0. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 cont (bit 0) ? continuous mode bit . t h e t i m e r w i l l r u n c o n t i n u o u s l y w h e n t h i s b i t i s s e t t o 1 . t h e t i m e r w i l l s t o p a f t e r e a c h c o u n t r u n a n d e n w i l l b e c l e a r e d i f t h i s b i t i s s e t t o 0 . t2compa (062h), - t i m e r m a x c o u n t c o m pare registers. t1compb (05ch) t1compa (05ah) t0compb (054h) t0compa (052h) these registers contain the m a xi m u m c ount value that is compared to th e re s p e c t i v e c o u n t re g i s t e r. t i m e r 0 and tim e r 1 have two of these compare registers each. if t i m e r 0 o r t i m e r 1 o r b o t h a re c o n fi g u re d t o c o u n t a n d c o m p a re fi rs t l y t o re g i ster a and then register b, the t m r o u t 0 o r tmro ut1 signals m a y be used to generate various duty-cycle wave for m s. tim e r 2 has only one compare register, t2compa. if o n e o f t h e s e t i m e r m a x c o u n t c o m p a re re g i s t e rs i s s e t t o 0 0 0 0 h , t h e r e s p e c t i v e t i m e r w i l l c o u n t f r o m 0000h to ffffh before generating an interrupt request. f o r e x a m p l e , a t i m e r c o n f i g u r e d i n t h i s m a n n e r with a 40mhz clock will interrupt every 6.5536 ms. t h e v a l u e o f t h e s e r e g i s t e r s i s u n d e f i n e d a t r e s e t . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 ?tc0 tc [15:0 ] ( bits 15-0) ? timer comp are value . t h e t i m e r w i l l c o u n t t o t h e v a l u e i n t h e r e s p e c t i v e register before resetting the count value to 0. t2cnt (060h) - t i m e r c ou n t r e g i s t e r s . t1cnt (058h) t0cnt (050h), these reg i sters are increm ented by one every fou r internal clock cycles if the relevant tim e r is enabled. t h e i n c r e m e n t o f t i m e r 0 a n d t i m e r 1 m a y also be controlled by external signals t m r i n 0 and tmrin1 respectively, or prescaled by tim e r 2. co m p a ri s o n s a re m a d e b e t w e e n t h e c o u n t re g i s t e rs a nd m a xcount registers and action taken dependent on achieving the m a xi m u m count. t h e v a l u e o f t h e s e r e g i s t e r s i s u n d e f i n e d a t r e s e t . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc15 ?tc0 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 tc [15:0 ] ( bits 15-0) ? timer count value . this register has the value of the current count of the r e l a t e d t i m e r t h a t i s i n c r e m e n t e d e v e r y f o u r t h p r o c e ssor clock in internal clocked m ode. alternatively, t h e r e g i s t e r i s i n c r e m e n t e d e a c h t i m e t h e t i m e r 2 m a x c ount is reached if using tim e r 2 as a prescaler. t i m e r 0 a n d t i m e r 1 m a y b e e x t e r n a l l y c l o c k e d b y t m r i n 0 a n d t m r i n 1 s i g n a l s . spicon (044h) - s e r i a l p o r t i n t e r r u p t c o n trol register. m a s t e r m o d e this register controls the operation of the asynchronous serial port interrupt sour ce (spi, bit 10 in of the interrupt request register) the value of this register is 001fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved res msk pr2-pr0 reserved (bits 15-5) ? s e t t o 0 . reserved (bit 4) ? s e t t o 1 . m s k ( b i t 3 ) m a s k . this bit, when 0, enables the serial port t o c a u s e a n i n t e r r u p t . w h e n t h i s b i t i s 1 , the serial port is prevented from generating an interrupt. pr2-pr0 (bits 2-0) ?priority . these bits define the priority of the serial por t i n t e r r u p t i n r e l a t i o n t o other interrupt signals. t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 a r e shown in the following table. p r i o r i ty le v e l priority p r 2 p r 0 (high) 0 000b 1 001b 2 010b 3 011b 4 100b 5 101b 6 110b (low) 7 111b wdcon (044h) ? watchdog timer interrupt c o n trol register. m a s t e r m o d e 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 these registers control the operation of the w a tchdog tim e r interrupt source. the valu e of this register is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved res msk pr2-pr0 reserved (bits 15-5) ? s e t t o 0 . reserved (bit 4) ? s e t t o 0 . m s k ( b i t 3 ) m a s k . this bit, when 0, enables the w a tchdog tim e r to cause an interrupt. w hen this bit is 1 prevents the w a t c hdog tim e r fro m g e n e ra t i n g a n i n t e rru p t . pr2-pr0 (bits 2-0) ?priority . these bits define the priority of the w a tchdog tim e r interrupt in relation to other interrupt s i g n a l s . t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 are shown in the above table (priority level). i4con (040h) ? i n t 4 c o n t r o l r e g i s t e r . m a s t e r m o d e this register controls the operation of the i n t 4 signal, which is only intended for use in fully nested m ode. the interrupt is assigned to type 10h. the value of the i4con regi ster is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ltm msk pr2-pr0 reserved (bits 15-5) ? s e t t o 0 . ltm (bit 4) ? l e v e l - t r i g g e r e d m o d e . the int4 interrupt m a y be edge or level triggered depending on the value of the bit. if l t m i s 1 , i n t 4 i s a c t i v e h i g h - l e v e l s e n s i t i v e i n t e r r u p t l . i f l t m i s 0 , i n t 4 i s a rising edge triggered interrupt. t h e i n t e r r u p t i n t 4 m u s t r e m a i n a c t i v e ( h i g h ) u n t i l s e r v i c e d . m s k ( b i t 3 ) m a s k . t h e i n t 4 s i g n a l c a n c a u s e a n i n t e r r u p t i f t h e m s k bit is 0. the int4 signal cannot c a u s e a n i n t e r r u p t i f t h e m s k bit is 1. pr2-pr0 (b it 2-0) ? p r i o r i t y . t h e s e b i t s d e f i n e t h e p r i o r i t y o f t h e s e r i a l p o r t i n t e r r u p t i n r e l a t i o n t o other interrupt signals. t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 a r e shown in the above table (priority level). i3con (03eh) ? i n t 2 / i n t 3 con t r o l r e g i s t e r . i2con (03ch), 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 m a s t e r m o d e int2 and int3 are designated as inte rrupt type 0eh and 0fh respectively. the i n t 2 a n d i n t 3 pins m a y be configured as the interrupt acknowledge pins inta0_n and i n t a 1 _ n respectively in cascade mode. the value of these registers is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved ltm msk pr2-pr0 reserved (bits 15-5) ? s e t t o 0 . ltm (bit 4) ? l e v e l - t r i g g e r e d m o d e the i n t 2 o r i n t 3 interrupt m a y be edge or level triggered depending on the value of this bit. if l t m is 1, i n t 2 o r i n t 3 i s a n a c t i v e h i g h l e v e l - s e n s i t i v e i n t e r r u p t . if l t m is 0, i n t 2 o r i n t 3 is a rising edge triggere d interrupt. t he interrupt i n t 2 o r i n t 3 must remain a c t i v e ( h i g h ) u n t i l a c k n o w l e d g e d . m s k ( b i t 3 ) m a s k . t h e i n t 2 o r i n t 3 s i g n a l c a n c a u s e a n i n t e r r u p t i f t h e m s k bit is 0. the i n t 2 o r i n t 3 signal cannot cause an interrupt if the m s k bit is 1. the interrupt ma sk register has a duplicate o f t h i s b i t . pr2-pr0 (b it 2-0) ? p r i o r i t y . these bits define the priority of the serial port interrupt i n t 2 o r i n t 3 i n relation to other interrupt si g n a l s . t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 are shown in the above table (priority level). i1con (03ah) ? i n t 0 / i n t 1 c o n t r o l r e g i s t e r . i0con (038h), ( m a s t e r m o d e ) iint0 and int1 are designated as inte rrupt type 0ch and 0dh respectively. the i n t 2 a n d i n t 3 pins m a y be configured as the interrupt acknowledge pins i n t a 0 a n d i n t a 1 r e s p e c t i v e l y , the interrupt acknowledge signals for i n t 0 and i n t 1 in cascade m ode. the value of these registers is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sfnm c ltm msk pr2-pr0 reserved (bits 15-7) ? s e t t o 0 . spnm (bit 6) ? special fully nested mode . t h i s b i t e n a b l e s f u l l y n e s t e d m o d e f o r i n t 0 o r i n t 1 w h e n s e t t o 1 . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 c ( b i t 5 ) ? cascade mode . t h i s b i t e n a b l e s c a s c a d e m o d e f o r i n t 0 o r i n t 1 w h e n s e t t o 1 . ltm (bit 4) ? l e v e l - t r i g g e r e d m o d e . the i n t 0 o r i n t 1 interrupt m a y be edge or level triggered depending on the value of the bit. if l t m is 1, int0 o r i n t 1 i s a n a c t i v e h i g h l e v e l - s e n s i t i v e i n t e r r u p t . if l t m is 0, i n t 0 o r i n t 1 is a rising edge triggere d interrupt. t he interrupt i n t 0 o r i n t 1 must remain a c t i v e ( h i g h ) u n t i l a c k n o w l e d g e d . m s k ( b i t 3 ) m a s k . t h e i n t 0 o r i n t 1 s i g n a l c a n c a u s e a n i n t e r r u p t i f t h e m s k bit is 0. the i n t 0 o r i n t 1 signal cannot cause an interrupt if the m s k bit is 1. the interrupt ma sk register has a duplicate o f t h i s b i t . pr2-pr0 (b it 2-0) ? p r i o r i t y . these bits define the priority of the serial port interrupt i n t 0 o r i n t 1 i n relation to other interrupt si g n a l s . t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 are shown in the above table (priority level). tcucon (032h) - t i m e r c o n t ro l u n i t interrupt c o n t r o l r e g i s t e r . m a s t e r m o d e t h e t h r e e t i m e r s h a v e t h e i r i n t e rrupts assigned to types 08h, 12h, a nd 13h and are conf igured by this r e g i s t e r . the value of this register is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2-pr0 reserved (bits 15-4) ? s e t t o 0 . m s k ( b i t 3 ) i n t e r r u p t m a s k . a n i n t e r r u p t s o u r c e m a y c a u s e a n i n t e r r u p t i f t h e m s k b i t i s 0 . t h e interrupt source cannot caus e a n i n t e r r u p t i f t h e m s k bit is 1. the interrupt mask register has a duplicate of this bit. pr2-pr0 (b it 2-0) ? p r i o r i t y . t h e s e b i t s d e f i n e t h e p r i o r i t y o f t h e s e r i a l p o r t i n t e r r u p t i n r e l a t i o n t o other interrupt signals. t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 a r e shown in the above table (priority level). t 2 i n t c o n ( 0 3 a h ) - t i m e r int e r r u p t c o n trol register. t 1 i n t c o n ( 0 3 8 h ) t 0 i n t c o n ( 0 3 2 h ) slave mode t h e t h re e t i m e rs , t i m e r2 , t i m e r1 , a n d t i m e r0 , e a c h h a v e an interrupt control regi s t e r , w h e r e a s i n m a s t e r m o d e a l l t h r e e a r e m a s k e d a n d p r i o ritized in one register (tcucon). 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 the value of these registers is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 - pr0 reserved (bits 15-4) ? s e t t o 0 . m s k ( b i t 3 ) m a s k . any of the interrupt sources m a y c a u s e a n i n t e r r u p t i f t h e m s k bit is 0. the interrupt sources cannot cau se an interrupt if the m s k bit is 1. the interrupt mask register has a duplicate of this bit. pr2-pr0 (b it 2-0) ? p r i o r i t y . these bits define the priority of the s e r i a l p o r t i n t e r r u p t s i n r e l a t i o n t o other interrupt signals. t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 a r e shown in the above table (priority level). dma1con/int6con (036h) ? dma a n d int e r r u p t c o n trol register. d m a 0 c o n / i n t 5 c o n ( 0 3 4 h ) m a s t e r m o d e the dma0 and dma1 interrupts have interrupt t ype 0ah and 0bh respectively. these pins are configured as external interrupts or d m a re q u e s t s i n t h e r e s p e c t i v e dma control register. the value of these registers is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 - pr0 reserved (bits 15-4) ? s e t t o 0 . m s k ( b i t 3 ) m a s k . any of the interrupt sources m a y c a u s e a n i n t e r r u p t i f t h e m s k bit is 0. the interrupt sources cannot cau se an interrupt if the m s k bit is 1. the interrupt mask register has a duplicate of this bit. pr2-pr0 (b its 2-0) ? priority . t h e s e b i t s d e f i n e t h e p r i o r i t y o f t h e s e r i a l p o r t i n t e r r u p t s i n r e l a t i o n t o other interrupt signals. t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 a r e shown in the above table (priority level). dma1con/int6 (036h) ? dma a n d int e r r u p t c o n t r o l r e g i s t e r . dma0con/int5 (034h) slave mode t h e t w o d m a c o n t r o l r e g i s t e r s m a i n t a i n t h e i r o r i g i n a l functions and addressing that they possessed in m a s t e r m o d e . t h e s e p i n s a re c o n fi g u re d a s e x t e rn a l i n t e r r u p t s o r d m a r e q u e s t s i n t h e r e s p e c t i v e d m a co n t ro l re g i s t e r. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 the value of these registers is 000fh at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved msk pr2 - pr0 reserved (bits 15-4) ? s e t t o 0 . m s k ( b i t 3 ) m a s k . any of the interrupt sources m a y c a u s e a n i n t e r r u p t i f t h e m s k bit is 0. the interrupt sources cannot cau se an interrupt if the m s k bit is 1. the interrupt mask register has a duplicate of this bit. pr2-pr0 (b its 2-0) ? priority . t h e s e b i t s d e f i n e t h e p r i o r i t y o f t h e s e r i a l p o r t i n t e r r u p t s i n r e l a t i o n t o other interrupt signals. t h e i n t e r r u p t p r i o r i t y i s t h e l o w e s t a t 7 a t r e s e t . t h e v a l u e s o f pr2 ?pr0 a r e shown in the above table (priority level). intsts (0 30h) ? int e r r u p t st a t u s register. m a s t e r m o d e t h e i n t e r r u p t s t a t u s r e g i s t e r c o n t a i n s t h e i n t e r r u p t request status of each of t h e t h r e e t i m e r s , t i m e r 2 , t i m e r1 , a n d t i m e r0 . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dhlt reserved tmr2 - tmr0 d h l t ( b i t 1 5 ) d m a h a l t . d m a a c t i v i t y i s h a l t e d w h e n t h i s b i t i s 1 . i t i s s e t t o 1 a u t o m a t i c a l l y when any non-m a skable interrupt occurs and is clear ed to 0 when an iret instruction is executed. i n t e r r u p t h a n d l e r s a n d o t h e r t i m e c r itical software m a y modify this bit directly to disable dma t r a n s f e r s . h o w e v e r , t h e d h l t bit should not be modified by soft w a r e i f t h e t i m e r i n t e r r u p t s a r e enabled as the function of this register as an in terrupt request register f o r t h e t i m e r s w o u l d b e c o m p r o m i s e d . reserved (bits 14-3) t m r [ 2 :0 ] ( b i t 2 -0 ) ? t i m e r i n t e r r u p t r e q u e s t . a p e n d i n g i n t e r r u p t r e q u e s t i s i n d i c a t e d b y t h e respective tim e r, when a ny of t h e s e b i t s i s 1 . ( n . b . t h e tmr b i t i n t h e r e q s t register is a logical or o f t h e s e t i m e r i n t e rru p t re q u e s t s ) slave mode when nonmaskable interrupts occur th e i n t e r r u p t s t a t u s r e g i s t e r c o n t r o ls dma operation and the interrupt r e q u e s t s t a t u s o f e a c h o f t h e t h r e e timers, tim e r2, tim e r1, and tim e r0. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dhlt reserved tmr2 - tmr0 dhlt ( bit 15) ? dma halt. d m a a c t i v i t y i s h a l t e d w h e n t h i s b i t i s 1 . i t i s s e t t o 1 a u t o m a t i c a l l y when any non-m a skable interrupt occurs and is clear ed to 0 when an iret instruction is executed. reserved (bits 14-3) t m r [ 2 :0 ] ( b i t 2 -0 ) ? t i m e r i n t e r r u p t r e q u e s t . a p e n d i n g i n t e r r u p t r e q u e s t i s i n d i c a t e d b y t h e respective tim e r, when a ny of t h e s e b i t s i s 1 . ( n . b . t h e tmr b i t i n t h e r e q s t register is a logical or o f t h e s e t i m e r i n t e rru p t re q u e s t s . ) reqst (02 e h) ? i n t e r r u p t r e q ue st register. m a s t e r m o d e t h i s i s a r e a d - o n l y r e g i s t e r a n d s u c h a r e a d r e s u l t s i n t h e s t a t u s o f t h e i n t e r r u p t r e q u e s t b i t s presented to t h e i n t e r r u p t c o n t r o l l e r . the reqst register is undefined on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e s e r v e d s p i w d i 4 i 3 i 2 i 1 i o d 1 - d 0 r e s t m r reserved (bits 15 ?11) s p i (b i t 1 0 ) s e r i a l p o r t in t e r r u p t r e q u e s t . t h i s i s t h e s e r i a l p o r t i n t e r r u p t s t a t e a n d w h e n e n a b l e d i s t h e l o g i c a l o r o f a l l t h e s e r i al port 0 inte r r u p t s o u r c e s : - thre, rdr, brki, fer, per, a n d o e r . w d (b i t 9 ) w a t c h d o g t i m e r in t e r r u p t r e q u e s t . t h i s i s t h e w a t c h d o g i n t e rru pt state and indicates that an interrupt is pending when it is a 1. i [4:0 ] (bits 8 - 4) interrupt requests . setting any of these bits to 1 i n d i c a t e s t h a t t h e r e l e v a n t interrupt has a pending interrupt. d1-d0 (bit 3:2) dma channel interrupt 6 request . s e t t i n g e i t h e r b i t t o 1 i n d i c a t e s t h a t e i t h e r t h e respective d m a channel has a pending interrupt. reserved (bit 1) t m r ( b i t 0 ) ? timer interrupt request . t h i s i s t h e t i m e r i n t e r r u p t s t a t e a n d i s t h e l o g i c a l o r o f t h e t i m e r i n t e r r u p t r e q u e s t s . s e t t i n g t h i s b i t t o 1 i n d i c a t e s t h a t t h e t i m e r c o n t r o l u n i t h a s a p e n d i n g i n t e r r u p t . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 slave mode t h i s i s a r e a d - o n l y r e g i s t e r a n d s u c h a r e a d r e s u l t s i n t h e s t a t u s o f t h e i n t e r r u p t r e q u e s t b i t s presented to t h e i n t e r r u p t c o n t r o l l e r . t h e s t a t u s o f these bits is available wh en this register is read. when an internal interrupt request ( d1, d0, tm r2, tmr1 , o r tmr0 ) o c c u r s , t h e r e s p e c t i v e b i t i s s e t t o 1 . the internally generated interrupt acknowledge resets these bits. the reqst register contains 0000h on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1 d0 res tmr0 reserved (bits 15 ?6) t m r 2 ( b i t 5 ) i n t e r r u p t r e q u e s t s . s e tting this bit to 1 indicates that tim er 2 has a pending interrupt. t m r 1 ( b i t 4 ) i n t e r r u p t r e q u e s t s . s e tting this bit to 1 indicates that tim er 1 has a pending interrupt. d1:d0 (bits 3:2) dma channel interrupt request. setting either bit to 1 i ndicates that the resp ective dma channel has a pending interrupt. reserved (bit 1) t m r 0 ( b i t 0 ) ? timer0 interrup t request. setting this bit to 1 indica t e s t h a t t i m e r 0 h a s a p e n d i n g i n t e r r u p t . inserv (02ch) ? i n - s e r v i c e register. m a s t e r m o d e t h e i n t e rru p t c o n t ro l l e r s e t s t h e b i t s i n t h i s re g i s t e r w h e n t h e i n t e rru p t i s t a k e n . w r i t i n g t h e c o rre s p o n d i n g i n t e r r u p t t y p e t o t h e e n d - o f - i n t e r r u p t ( e o i ) r e g i s t e r c l e a r s each of these bits. w h e n o n e o f t h e s e b i t s i s s e t , a n i n t e r r u p t r e q u e s t w i l l n o t b e g e n e r a t e d b y t h e m i c r o c o n t r o l l e r f o r t h e r e s p e c t i v e s o u r c e . t h i s p r e v e n t s a n i n t e r r u p t f r o m i n t e r r u p t i n g i t s e l f i f i n t e r r u p t s a r e e n a b l e d i n t h e i s r . this restriction is bypassed in fully s pecial fully nested m ode for the int0 and int1 sources. the inserv register contains 0000h on reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e s e r v e d s p i w d i 4 i 3 i 2 i 1 i o d 1 d 0 r e s t m r reserved (bits 15 ?11) s p i (b i t 1 0 ) s e r i a l p o r t in t e r r u p t r e q u e s t . this is the s e r i al port 0 interrupt state . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 wd (bit 9) ?watchdog t i mer interrupt in-service request. t h i s b i t i s t h e i n - s e r v i c e s t a t e o f t h e watchdog tim e r . i [4:0 ] (bits 8 - 4) interrupt requests. setting any of these bits to 1 i n d i c a t e s t h a t t h e r e l e v a n t interrupt has a pending interrupt. d1-d0 (bit 3:2) dma channel interrupt in-service. t h i s b i t i s t h e in -s e r v i c e state of the respective dma channel. reserved (bit 1) t m r ( b i t 0 ) ? timer interrupt request . t h i s i s t h e t i m e r i n t e r r u p t s t a t e a n d i s t h e l o g i c a l o r o f t h e t i m e r i n t e r r u p t r e q u e s t s . s e t t i n g t h i s b i t t o 1 i n d i c a t e s t h a t t h e t i m e r c o n t r o l u n i t h a s a p e n d i n g i n t e r r u p t . slave mode this is a read-only register and such a r e a d s u p p l i e s t h e s t a t u s o f t h e i n terrupt request bits presented to the interrupt controller. when an internal interrupt request ( d1, d0, tm r2, tmr1 , and tmr0 ) o c c u r s , t h e r e s p e c t i v e b i t i s s e t t o 1. the internally generated interr upt acknowledge rese ts these bits. the r e q s t register contains 0000h on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1 d0 res tmr0 reserved (bits 15 ?6) t m r 2 (b i t 5 ) t i m e r 2 in t e r r u p t in s e r v i c e . t i m e r 2 is being serviced when this bit is set to 1. t m r 1 (b i t 4 ) t i m e r 1 in t e r r u p t in s e r v i c e . t i m e r 1 i s b e i n g s e r v i c e d w h e n t h i s b i t i s s e t t o 1 . d1-d0 (bit 3:2) dma channel interrupt in service. t h e r e s p e c t i v e d m a c h a n n e l i s b e i n g s e r v i c e d w h e n t h i s b i t i s s e t t o 1 . reserved (bit 1) t m r 0 ( b i t 0 ) ? t i m e r i n t e r r u p t i n s e r v i c e . t i m e r 0 i s b e i n g s e r v i c e d w h e n t h i s b i t i s s e t t o 1 . primsk (02ah) ? p r i o r i t y m a s k register. ma s te r a n d s l a v e mo d e t h i s r e g i s t e r c o n t a i n s a v a l u e t h a t s e t s t h e m i n i m u m priority level at which an interrupt can be generated b y a m a s k a b l e i n t e r r u p t . the primsk register contains 0007h on reset 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 prm2 ?prm0 reserved (bits 15 ? 3) ? set to 0 . prm 2-prm0 (bits 2 - 0) priority field mask. t h i s t h r e e - b i t f i e l d s e t s t h e m i n i m u m p r i o r i t y n e c e s s a ry fo r a m a s k a b l e i n t e rru p t to generate an interrupt. any m a skable interrupt with a num e rically higher value than that cont ained by these three bits is m a sked. p r i o r i ty le v e l priority p r 2 p r 0 (high) 0 0 0 0b 1 0 0 1b 2 0 1 0b 3 0 1 1b 4 1 0 0b 5 1 0 1b 6 1 1 0b (low) 7 1 1 1b any unm a sked interrupt can generate an i n t e r r u p t i f t h e p r i o r i t y l e v e l i s set to 7. on the other hand, if t h e p r i o r i t y l e v e l i s s e t t o s a y 4 , o n l y u n m a s k e d i n t e r r u p t s w i t h a p r i o r i t y o f 0 t o 5 a r e p e r m i t t e d t o generate interrupts. i m a s k ( 0 2 8 h ) ? i nterrupt mask register. m a s t e r m o d e t h e i n t e r r u p t m a s k r e g i s t e r i s r e a d / w r i t e . s e t t i n g a b i t i n t h i s r e g i s t e r i s e f f e c t i v e l y t h e s a m e a s s e t t i n g t h e m s k bit in the corresponding interrupt control register. setting a bit to 1 m a sks the interrupt. the interrupt request is enabled when the corresponding bit is set to 0. the imask regis t er co ntains 07fdh on reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r e s e r v e d s p i w d i 4 i 3 i 2 i 1 i 0 d 1 - d 0 r e s t m r reserved (bits 15 ?11) spi (bit 10) ?serial port interrupt mask . setting this bit to 1 is an indication that the asynchronous serial port interrupt is m a sked. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 wd (bit 9) ?watchdog t i mer interrupt in-service request . s e t t i n g t h i s b i t t o 1 i s a n i n d i c a t i o n t h a t t h e w a t c h d o g t i m e r i n t e r r u p t i s m a s k e d . i [4:0 ] (bits 8 - 4) interrupt mask . s e tting any of these b i t s t o 1 i s a n i n d i c a t i o n t h a t t h e r e l e v a n t interrupt is m a sked. d1-d0 (bit 3:2) dma channel interrupt mask . s e t t i n g t h i s b i t t o 1 i s a n i n d i c a t i o n t h a t t h e r e s p e c t i v e dma channel interrupt is m a sked. reserved (bit 1) t m r ( b i t 0 ) ? t i m e r i n t e r r u p t m a s k . w h e n s e t t o 1 , i t i n d i c a t e s t h a t t h e t i m e r c o n t r o l u n i t i n t e r r u p t i s m a sked. slave mode t h e i n t e r r u p t m a s k r e g i s t e r i s r e a d / w r i t e . s e t t i n g a b i t i n t h i s r e g i s t e r i s e f f e c t i v e l y t h e s a m e a s s e t t i n g t h e m s k bit in the corresponding interrupt c ontrol register. setting a bit to 1 m a sks the interrupt request. the interrupt request is enabled when the corresponding bit is set to 0. the imask register co ntains 003dh on reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved tmr2 tmr1 d1 d0 res tmr0 reserved (bits 15 ?6) tmr2 (bit 5) timer2 interrupt mask . this bit provides an indication of t h e s t a t e o f t h e m a s k b i t i n t h e t i m e r i n t e r r u p t c o n t r o l r e g i s t e r . w h e n i t i s s e t t o 1 , i t i n d i c a t e s t h a t t h e i n t e r r u p t r e q u e s t i s m a sked. tmr1 (bit 4) timer1 interrupt mask . this bit provides an indication of t h e s t a t e o f t h e m a s k b i t i n t h e t i m e r i n t e r r u p t c o n t r o l r e g i s t e r . w h e n i t i s s e t t o 1 , i t i n d i c a t e s t h a t t h e i n t e r r u p t r e q u e s t i s m a sked. d1-d0 (bit 3:2) dma channel interrupt mask . this bit provides an indi cation of the state of the m a s k b i t i n t h e r e s p e c t i v e d m a c h a n n e l i n t e r r u p t c o n t r o l r e g i s t e r . w h e n i t i s s e t t o 1 , i t i n d i c a t e s t h a t the interrupt request is m a sked. reserved (bit 1) t m r 0 ( b i t 0 ) ? t i m e r i n t e r r u p t m a s k . this bit provides an indication of t h e s t a t e o f t h e m a s k b i t i n t h e t i m e r i n t e r r u p t c o n t r o l r e g i s t e r . w h e n i t i s s e t t o 1 , i t i n d i c a t e s t h a t t h e i n t e r r u p t r e q u e s t i s m a sked. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 pollst (0 26h) ? poll st a t u s re g i s t e r. m a s t e r m o d e this register reflects the current state of the poll regi ster and can be read w ithout affecting its contents. however, when the poll register is read, it causes the current in terrupt to be acknowledged and be replaced by the next interrupt. the poll status register is read-only. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ireq r e s e r v e d s4 ?s0 ir e q (b i t 1 5 ) in t e r r u p t r e q u e s t . t h i s b i t i s s e t t o 1 w h e n a n i n terrupt is pending. and during this s t a t e , t h e s 4 - s 0 bits contain valid data. reserved (bits 14-6) s e t t o 0 s [4:0 ] (bit 4-0) ? p o l l s t a t u s . these bits show the interrupt t ype of the highest priority pending i n t e r r u p t . t h e i n t e r r u p t s e r v i c e r o u t i n e d o e s not begin execution autom a tically w i t h t h e i s b i t s e t . r a t h e r , t h e application software m us t ex ecute the appropriate isr. poll (024h) ? p o l l r e g i s t e r . m a s t e r m o d e w h e n t h e p o l l r e g i s t e r i s r e a d , i t c a u s e s t h e c u rre n t i n t e rru p t t o b e a c k n o w l e d g e d a n d b e re p l a c e d b y t h e next interrupt. the poll status register reflects the current state of the po ll register and can be read without affecting its contents. the poll r e gister is read-only. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ireq reserved s4 ?s0 ir e q (b i t 1 5 ) in t e r r u p t r e q u e s t . t h i s b i t i s s e t t o 1 w h e n a n i n terrupt is pending. and during this s t a t e , t h e s 4 - s 0 bits contain valid data. reserved (bits 14-6) s [4:0 ] (bit 4-0) ? p o l l s t a t u s . these bits show the interrupt t ype of the highest priority pending i n t e r r u p t . e o i ( 0 2 2 h ) ? e nd - o f - i nterrupt register. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 m a s t e r m o d e the in service flags of the in-serv i ce regis t er ar e r e s e t w h e n a w r i t e i s m a d e t o t h e e o i r e g i s t e r . t h e i n t e r r u p t s e r v i c e r o u t i n e ( i s r ) s h o u l d w r i t e t o t h e e o i t o r e s e t t h e i s b i t , i n t h e i n - s e r v i c e r e g i s t e r , for the interrupt before executing an iret instruc tion that ends an inte r r u p t s e r v i c e r o u t i n e . t h e s p e c i fi c e o i re s e t i s t h e p re f erred m e thod for resetti ng the is bits as it is m ost secure. the eoi register is write-only. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nspec reserved s4 ?s0 n s p e q ( b i t 1 5 ) n o n - s p e c i f i c e o i . t h i s b i t i s s e t t o 1 a n o n - s p e c i f i c e o i a n d w h e n s e t t o 0 i t indicates the specific eo i. reserved (bits 14-5) s [4:0 ] (bit 4-0) ? sourc e interrupt t y pe . these bits show the interrupt type of the highest priority pending interrupt. e o i ( 0 2 2 h ) ? specific e nd - o f - i nterrupt register. slave mode an in service flag of a specific prio r i t y , i n t h e i n - s e r v i c e r e g i s t e r , i s r e s e t w h e n a w r i t e i s m a d e t o t h e eoi register. a t h r e e - b i t u s e r s u p p l i e d p r i o r i t y - l e v e l v a l u e t h a t p o i n t s t o t h e i n -s e rv i c e b i t t h a t i s t o b e r e s e t . w r i t i n g t h i s v a l u e t o t h i s r e g i s t e r r e s e t s t h e s p e c i f i c b i t . the eoi register is write only and undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 l2 ?l0 reserved (bits 15-3) ? write as 0. l[2:0 ] (bit 2-0) ?interrupt type . the priority or the is (interrupt se r v i c e ) b i t t o b e r e s e t i s e n c o d e d i n t h e s e t h r e e b i t s . w r i t i n g t o t h e s e b i t s c a u s e d t h e i s s u a n c e o f a n e o i f o r t h e i n terrupt type. see table 3 - interrupt types. intvec (020h) int errupt v e c t o r r e g i s t e r . slave mode 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 t h e c p u s h i f t s l e f t 2 b i t s ( m u l t i p l i e s b y 4 ) a n 8 - b i t i n t e r r u p t t y p e , g e n e r a t e d b y t h e i n t e r r u p t c o n t r o l l e r , t o p r o d u c e a n o f f s e t i n t o t h e i n t e r r u p t v e c t o r t a b l e . the intvec register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 t4 ?t0 0 0 0 reserved (bits 15-8) re a d a s 0 . t [4:0 ] (bits 7-3) ?interrupt type . these five b its con t ain the fi ve m ost significant bits of the i n t e r r u p t t y p e s u s e d f o r t h e i n t e r n a l i n t e r r u p t t y p e . t h e l e a s t s i g n i f i c a n t t h r e e b i ts of the interrupt type are supplied by the interrupt contro ller, as set by the priority level of the interrupt request. reserved (bits 2-0) ?re ad as 0. ssr (018h) ? s ynchronous s e r i a l r eceive register. this register holds the serial data received on the ssi port. the value of the ssr register is undefined at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sr7-sr0 reserved (bits 15-8) ? r e s e r v e d b i t s . sr[ 7:0 ] (bits 7-0) ?dat a received o ver the sda t a pin. ssd0 (016h) ? s ynchronous s e r i a l t r a n s m i t registers. ssd0 (014h) t h e s e r e g i s t e r s h o l d t h e d a t a t o b e t r a n s m i t t e d b y t h e s s i p o r t s . t h e v a l u e o f t h e s e r e g i s t e r s i s u n d e f i n e d a t r e s e t . 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sd7-sd0 reserved (bits 15-8) ? r e s e r v e d b i t s . sd[ 7:0 ] ( bits 7-0) ?data to be trans mitted ov er the sdata pin. ssc (012h) ? s ynchronous s e r i a l c ontrol register. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 this register controls the operation of the sden1 a n d sden0 outputs and the baud rate of the ssi port. the sden1 and sden0 outputs are held high when the respective b i t i s s e t t o 1 , b u t i n t h e e v e n t t h a t b o t h d e 1 and d e 0 are set to 1 then only sden0 will be held high. the value of the ssr register is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved sclkdiv res de1-de0 reserved (bits 15-6) ? r e s e r v e d b i t s . sclkdiv (bits 5-4) ? sclk divide. these bits set th e sclk freque ncy. sclk is the result of dividing the internal processor clock by 2, 4, 8, or 16 as in the following table. s c l k d i v s c l k f r e q u e n c y d i v i d e r 00b processor clock /2 01b processor clock /4 10b processor clock /8 11b processor clock /16 res (bits 3-2) ?reserved bits. de1 (bit1) - sden1. the sden1 bit is held high when this b i t i s s e t t o 1 a n d sden1 is held low w h e n t h i s b i t i s s e t t o 0 . d e 0 (b i t 0 ) s d e n0 . the sden0 bit is held high when this b i t i s s e t t o 1 a n d sden0 is held low w h e n t h i s b i t i s s e t t o 0 . sss (010h) ? s ynchronous s e r i a l s tatus register. this is a read only register that i n d i c a t e s t h e s t a t e o f t h e s s i p o r t . the value of the ssr register is 0000h at reset. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved re/te dr/dt pb reserved (bits 15-3) ? r e s e r v e d b i t s . re/te (bit 2) ?receive/transmit er ror detect. t h i s b i t i s s e t t o 1 w h e n a read of the synchronous serial received regis t er or a write t o o n e o f t h e t r a n s m i t r e g i s t e r i s d e t e c t e d w h i l e t h e i n t e rfa c e i s b u s y 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 ( p b = 1). t his bit is reset to 0 when the s d e n output is not active (de1-de0 i n t h e s s c r e g i s t e r a r e 00h). dr/dt (bit 1) ? data receive/trans mit complete. this bit is set to a 1 when the transm ission of data bit 7 is completed (sclk rising ed g e ) d u r i n g a t r a n s m i t o r r e c e i v e o p e ration. this bit is reset by a read of the ssr register, when e ither the ssd0 or ssd1 register is written, when the sss register is r e a d ( u n l e s s t h e s s i c o m p l e t e s a n o p e r a t i o n a n d s e t s the bit in the sam e cycle), or when both sden0 and sden1 becom e inactive. p b ( b i t 0 ) s s i p o r t b u s y . t h i s b i t i n d i c a t e s t h a t a d a t a t r a n s m i t o r r e c e i v e i s o c c u r r i n g w h e n i t i s s e t t o 1 . w h e n s e t t o 0 i t i n d i c a t e s t h a t t h e p o r t i s r e a d y t o t r a n s m i t o r r e c e i v e d a t a . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m c l o c k a n d p o w e r m a n a g e m e n t a phase-lock-loop (pll ) and a second programm a ble system clock output (clk o u t b) a re i n c l u d e d i n the clock and power m a nagem e nt unit. the internal cl ock is the sam e frequency as the crystal but with a duty cycle of 45% - 55 %, as a worse case, generate d by the pll obviating the need for an x2 external clock. a power-on reset (por) resets the pll. f i g u r e 2 . c r y s t a l c o n f i g u r a t i o n system clocks if re q u i re d , t h e i n t e rn a l o s c i l l a t o r c a n be driven by an external clock s ource that should be connected to x1, leaving x2 unconnected. the clock outputs clkouta and c l k o u t b m a y be e nabled or disabled individually (power-save control register (pdcon) bits (11 ? 8)). t h e s e c l o c k c o n t r o l b i t s a l l o w o n e c l ock output to run at pll frequency and the other to run at th e power-save frequency. f i g u r e 3 . o r g a n i z a t i o n o f c l o c k c r y s t a l c 1 c 2 x 2 x 1 a m 1 8 6 / 1 8 8 e m recommended range of v a l u e s f o r c 1 and c 2 a r e : c 1 = 1 5 p f + / - 2 0 % c 2 = 2 2 p f + / - 2 0 % p l l power-save d i v i s o r ( / 2 t o / 1 2 8 ) mux mux p r o c e s s o r i n t e r n a l c l o c k t i m e delay 6 + / - 2 . 5 n s d ri v e e n a b l e d ri v e e n a b l e x 1 , x 2 c l k o u t a c l k o u t b
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 power-sa ve mode t h e o p e r a t i o n o f t h e c p u a n d p e r i p h e r a l s o p e r a t e a t a slower clock frequency when in power save m ode reducing power consumption and therm a l dissipation. should an interrupt o c c u r, t h e m i c ro c o n t ro l l e r r e t u r n s t o i t s n o r m a l o p e r a t i n g f r e q u e n c y a u t o m a t i c a l l y o n t h e i n t e r n a l clock? next ri sing edge in t 3 . any clock dependent devices should be reprogramm e d fo r the changed in frequency during the power-save mode period. i n i t i a l i z a t i o n a n d r e s e t r e s _ n (reset), the highest prio rity interrupt, m ust be held low for 1m s dur ing power-up to initialize the m i crocontroller correctly. this operation m a kes the d e v i c e c e a s e a l l i n s t r u c t i on execution and local bus a c t i v i t y . t h e m i c ro c o n t o l l e r b e gins instruction execution at physical address ffff0h when r e s _ n b e c o m e s i n a c t i v e a n d a f t e r a n i n t e rnal processing i n t e r v a l w i t h ucs_n a s s e rt e d a n d t h re e w a i t s t a t e s . re s e t also sets up certain register s to predeterm i ned values and resets the w a tchdog tim er. r e se t c o n f i g u r a t i o n r e g i st e r the data on the address/data bus ( ad 15 ?ad0 for the am 186em and ao15 ?ao8 and ad7 ?ad0 f o r t h e a m 1 8 8 e m ) a r e w r i t t e n i n t o t h e r e s e t configuration register when reset is low. this data is system dependent and is held in the reset c onfiguration regi s t e r a f t e r r e s e t i s d e - a s s e rt e d . t h i s c o n fi g u ra t i o n d a t a m a y b e p l a c e d o n t h e a d d re s s / d a t a b u s b y u s i n g w e a k e x t e rn a l p u l l -u p a n d p u l l -d o w n re s i s t o r s o r applied to the bus by an external dr iver, as the processor does not driv e the bus during reset. it is a m e thod of s upplying the software with som e initial d a t a a f t e r a r e s e t ; f o r e x a m p l e , o p t i o n j u m p e r p o s i t i o n s . chip selects chip select generation is programma ble for m e mories and peripherals. p r o g r a m m i n g i s a l s o a v a i l a b l e t o produce ready and wait-state genera tion plus latched address bits a1 and a2 . f o r a l l m e m o ry a n d i/ o c y c l e s , t h e c h i p - s e l e c t l i n e s a r e a c t i v e w i t h i n t h e i r p r o g r a m m e d a r e a s , r e g a r d l e s s o f w h e t h e r t h e y a r e generated by the internal dma unit or the cpu. there are six chip selects outputs for m e m o r i e s a n d a f u r t h e r s i x f o r p e r i p h e r a l s w h e t h e r i n m e m o r y o r i / o space. the m e mory chip-selects are able to addre s s t h r e e m e m o r y r a n g e s , w h e r e a s t h e p e r i p h e r a l c h i p - s e l e c t s a re u s e d t o a d d re s s 2 5 6 -b y t e b l o c k s t h a t a re o ffs e t fro m a p ro g ra m m a b l e b a s e a d d re s s . w r i t i n g t o a c h i p -s e l e c t re g i s t e r e n a b l e s t h e re l a t e d l o g i c e v e n i n t h e e v e n t t h a t t h e p i n in question has another function, as for exam ple in the case that the pin is programmed to be a pio. c h i p s e le c t t i m i n g f o r n o r m a l t i m i n g , t h e ucs_n and l c s _ n o u t p u t s a r e a s s e r t e d w i t h t h e n o n - m u l t i p l e x e d a d d r e s s b u s . r e a d y a n d w a i t - s t a t e p r o g r a m m i n g each of the m e mory or peripheral chip-select lines can have a ready signal programm e d that can be the ardy o r s r d y signal. the chip-select control register s (umcs, lmcs, mmcs, pacs, and mpcs) have a single bit that selects if the external ready signal is to be used or not ( r 2 , bit 2). r1 & r0 (bits 1-0) in t h e s e re g i s t e rs c o n t ro l t h e n u m b e r o f w a i t -s t a t e s t h at are inserted during each access to a m e mory or 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 peripheral location (from 0 to 3) . the control registers for pcs3_n ?pcs0_n u t i l i z e t h r e e b i t s , r3, r1 ? r0 ( b i t s 3 , 1 0 ) t o p r o v i d e 5 , 7 , 9 , a n d 1 5 w a i t - s t a t e s i n a d d i t i o n t o t h e o r i g i n a l v a l u e s o f 0 3 w a i t s t a t e s . i n t h e c a s e w h e r e a n e x t e r n a l r e a d y h a s b e e n selected as req uired, i n t e r n a l l y p r o g r a m m e d w a i t - s t a t e s w i l l a l w a y s b e c o m p l e t e d b e f o r e t h e e x t e r n al r e a dy can f i nis h or extend a bus cycle. as an e x a m p l e , c o n s i d e r a s y s t e m i n w h i c h t h e n u m b e r o f w a i t - s t a t e s t o b e i n s e r t e d h a s b e e n s e t t o t h r e e . t h e e x t e r n a l r e a d y p i n i s s a m p l e d b y t h e p r o c e s s o r d u r i n g t h e fi rs t w a i t c y c l e . t h e a c c e s s i s c o m p l e t e d a ft e r seven cycles (4 cycles plus 3 wait-cy c l e s ) i f t h e r e a d y i s a s s e r t e d . a l t e r n a t i v e l y , i f t h e r e a dy is not asserted d u r i n g t h e f i r s t w a i t c y c l e t h e a c c e s s i s p r o l o n g e d u n t i l r e a d y i s a s s e r t e d a n d t w o m o r e w a i t - s t a t e s a r e inserted followed by t 4 . chip select ov erlap o v e r l a p p i n g c h i p s e l e c t s a r e t h o s e c o n f i g u r a t i o n s i n w h i c h m o re t h a n o n e c h i p -s e l e c t i s a s s e rt e d fo r t h e sam e physical address. f or exam ple, if pcs is confi gured in i/o space with lcs or any other ch ip select configured for m e m ory, address 00000h is not overlapping the chip select s . it i s n o t re c o m m e n d e d t h a t m u l t i p l e c h i p -s e l e c t s i g n a l s b e a s s e rt e d fo r t h e s a m e p h y s i c a l a d d r e s s , a l t h o u g h i t m a y b e i n e s c a p a b l e i n c e r t a i n s y s t e m s . i f t h i s i s t h e c a s e , t h e n a l l o v e r lapping chip-selects m ust have t h e s a m e e x t e r n a l r e a d y configuration and the sam e number of wait-st ates to be ins e rted into access cycles. i n t e r n a l s i g n a l s a r e e m p l o y e d t o a c c e s s t h e p e r i p h e r a l c o n t ro l b l o c k (p cb) a n d t h e s e s i g n a l s s e r v e a s c h i p selects that are configured with no wait-states an d no external ready. therefore, the p cb can be programm e d with addresses that overlap external chip-s e l e c t s o n l y i f t h e s e c h i p selects are configured in t h e s a m e m a n n e r . care should be exercised in th e use of the disable address ( d a ) b i t i n t h e l m c s o r u m c s r e g i s t e r s w h e n o v e r l a p p i n g a n a d d i t i o n a l c h i p - s e l e c t w i t h e i t h e r t h e l c s _ n o r ucs_n c h i p - s e l e c t s . s e t t i n g t h e d a b i t t o 1 p re v e n t s t h e a d d re s s fro m b e i n g d ri v e n o n t o t h e a d b u s fo r a l l a c c e s s e s fo r w h i c h t h e re s p e c t i v e c h i p - s e l e c t i s a c t i v e , i n c l u d i n g t h o s e a c c e s s e s f o r w h i c h t h e m u l t i p l e s e l e c t s a r e a c t i v e . the m c s _ n a n d pcs_n pins are dual-purpose pins, either as chip-selects or pi o inputs or outputs. h o w e v e r , t h e i r r e s p e c t i v e r e a d y a n d w a i t - s t a t e c o n f i g u r a t i o n s f o r t h e i r c h i p - s e l e c t f u n c t i o n w i l l b e i n effect no m a tter for which function th e s e t w o p i n s a re a c t u a l l y p ro g ra m m e d. this requires that even if t h e s e p i n s a re c o n fi g u re d a s p io a n d e n a b l e d ( by writing to the mmcs and mpcs registers for the m c s _ n chip -selects and to the pacs and mpcs registers for the pcs_n c h i p - s e l e c t s ) , t h e r e a d y a n d w a i t - s t a t e s e t t i n g s f o r t h e s e s i g n a l s m u s t a g r e e w i t h t h e s e ttings for any over-lapping chip -selects as if they had b e e n c o n f i g u r e d a s c h i p - s e l e c t s . even though pcs4_n i s n o t a v a i l a b l e a s a n e x t e r n a l p i n i t h a s ready and w a it-state logic and m ust therefore follow the rules for overlapping chip-selects. p c s 6 _ n and pcs5_n on the other hand have ready and wait- s t a t e l o g i c t h a t i s d i s a b l e d w h e n t h e s e pins are configured as address bits a2 and a1 r e s p e c t i v e l y . if the chip -s elect config uration rules are not follo wed, the processor m a y hang with the appearance of waiting for a ready signal even in a system in which ready ( a r d y o r srdy ) is always set to 1. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 upper memory chi p select the ucs_n c h i p - s e l e c t i s f o r t h e t o p o f m e m o r y . o n reset, the m i cro contro ller begins fetching and executing instructions at m e mory location ffff0h. as a result, upper m e mory is usually utilized for instruction m e mory. to this end, u c s _ n is active on reset and has a m e mory range of 64kbytes (f0000h to fffffh) as default along with external ready require d and three wait-states au tom a tically inserted. the lower boundary of ucs_n is programm able to provide ranges of 64kbytes to 512kbytes. low m e m o ry chip select the l c s _ n c h i p - s e l e c t i s f o r l o w e r m e m o r y . a s t h e i n t e r r u p t v e c t o r t a b l e i s a t t h e b o t t o m o f m e m o r y beginning at 00000h, this pin us usually utilized for control data m e m ory. unlike u c s _ n , this pin is i n a c t i v e o n r e s e t , b u t i t c a n b e activated by any read or write to the lmcs register. m i d r a n g e m e m o r y c h i p s e l e c t s there are four m i drange chip-selects, mcs3_n-mcs0_n , which m a y be used in a user-located m e mory block. the base address of the m e mory block m a y be located anywhere in th e 1 - m b y t e m e m o r y a d d r e s s s p a c e w i t h s o m e e x c e p t i o n s . t h e m e m o ry s p a c e s u s e d b y t h e ucs_n and l c s _ n chip-selects are excluded, a s a r e t h e pcs6_n, pcs5_n, and pcs3_n ?pcs0_n . if the p c s _ n chip-selects are m a pped to i/o space then the mcs address range can ove rlap the pcs address range. both the midrange mem ory chip se l e c t ( m m c s ) r e g i s t e r a n d t h e m c s a n d p c s a u x i l i a r y r e g i s t e r (mpcs) registers are used to program the four m i dra nge chip-selects. the mpcs register is used to configure the block size, whereas the mmcs register configures the base address, the ready condition, and the wait states of the m e m ory block acces sed by the m c s_n pin. the chip selects ( mcs3_n-mcs0_n) a re a c t i v a t e d b y p e rfo rm i n g a re a d o r write operation of the mmcs and mp cs registers. the assertion of the mcs outputs occur s with the s a me tim ing as the m ultiplex e d ad address bus ( a d 1 5 - a d 0 o r ao15-ao8 and ad7-ad0 ). t h e a19-a0 m a y b e u s e d f o r a d d r e s s s e l e c t i o n , b u t t h e t i m i n g w i l l b e d e l a y e d b y a h a l f c l o c k c y c l e o v e r t h e t i m i n g u s e d f o r t h e ucs_n and lcs_n. p e r i p h e r a l c h i p s e l e c t s there are six periphe r a l c h i p - s e l e c t s , pcs6_n, pcs5_n, and pcs3_n ?pcs0_n , that m a y be used within a user-defined m e m ory or i/o block. the base address of this user-def ined m e m ory bloc k can be located a n y w h e re w i t h i n t h e 1 -m b y t e m e m o ry a d d re s s s p ace except for the spaces associated with the u c s _ n , l c s _ n , and m c s _ n chip selects. or it m a y be pr ogramm e d to the 64kbyte i/o space. pcs4_n is not a v a i l a b l e . b o t h t h e p e r i p h e r a l c h i p s e l e c t (pacs) register and the mc s a n d p c s a u x i l i a r y r e g i s t e r ( m p c s ) r e g i s t e r s a r e u s e d t o p r o g r a m t h e s i x p e ri p h e ra l c h i p -s e l e c t s , pcs6_n, pcs5_n, and pcs3_n ?pcs0_n. the pacs register sets the base address, th e ready condition, and th e w a i t s t a t e s fo r t h e pcs3_n ?pcs0_n o u t p u t s . the mpcs register configures p c s 6 _ n a n d pcs5_n pins as either chip selects or address pins a1 a n d a2 r e s p e c t i v e l y . w h e n t h e s e p i n s a r e c h i p s e l e c t s t h e m p c s r e g i s t e r a l s o configures them as being active during m e mory or i/o bus cycles, a n d t h e i r r e a d y a n d w a i t s t a t e s . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 none of the pcs_n pins are active at reset. both the periphe ral chip select (pacs) register and the mcs a n d p c s auxiliary register (mpcs) registers m ust b e r e a d o r w r i t t e n t o a c t i v a t e t h e p c s _ n p i n s a w s c h i p s e l e c t s . pcs6_n a n d pcs5_n m a y be program m e d to have 0 to 3 wait-states, whereas pcs3_n ? pcs0_n m a y b e programm e d to have these and 5, 7, 9, and 15 wait-states. r e f r e s h c o n t r o l the refresh control unit (rcu) generates refresh bus cycles. the rcu generates a m e mory read request after a programma b l e p e r i o d o f t i m e t o t h e bus interface unit. the e n a b i t i n t h e e n a b l e rcu re g i s t e r (e d ra m ) e n a b les refresh cycles, operating off the processor internal clock. if the pr o c e s s o r i s i n p o w e r - s a v e m o d e , t h e r c u m u s t b e r e c o n f igured for the new clock r a t e . if t h e hlda p i n i s a s s e r t e d w h e n a r e f r e s h r e q u e s t i s i n i t i a t e d (i n d i c a t i n g a b u s h o l d c o n d i t i o n ) , t h e processor disables the h l d a p i n t o a l l o w a re fre s h c y c l e t o b e p e rf o r m e d . t h e e x t e r n a l c i r c u i t b u s m a s t e r m u s t d e a s s e r t t h e h o l d signal for at least one clock period to p e rm i t t h e e x e c u t i o n o f t h e re fre s h c y c l e . in t e r r u p t c o n t r o l interrupt requests originate from a va riety of internal and external sour ces that are arrange d b y t h e i n t e r n a l interrupt controller in prio ri t y o rd e r a n d p re s ented one by one to the processor. s i x e x t e r n a l i n t e r r u p t s o urces, five m a skable ( i n t 4 - i n t 0 ) and one nonm as kable (nmi), are connected to the processor and six internal in terrupt sources (three tim e rs, two dma channels, and the asynchronous serial port that are not brought out to external pins). the five external m a skable interrupt request pins can be used as direct interr upt requests. however, should m ore interrupts be needed, i n t 3 - i n t 0 m a y be with an external interrupt controller of the 82c59a type. by programm i ng the internal interrupt controll e r t o s l a v e m o d e , a n e x t e rnal 82c59a com p atible interrupt controller can be used as the system master. interrupt nesting c a n b e u s e d i n a l l c a s e s t h a t p e rm i t interrupts of a higher priority to in terrupt those of a lower priority. when an interrupt is acce pted, other interrupts are disabled, but m a y be re-enabled by setting the interrupt e n a b l e f l a g ( i f ), i n t h e p ro c e s s o r s t a t u s f l a g s re g i s t e r, d u r i n g t h e i n t e r r u p t s e r v i c e r o u t i n e ( i s r ) . s e t t i n g i f p e rm i t s i n t e rru p t s o f e q u a l o r g r e a t e r p r i o r i t y t o i n t e r r u p t the currently running isr. further interrupts from the sam e source will be bl ocked until the corresponding b i t i n t h e i n - s e r v i c e re g i s t e r (in s e rv ) i s c l e a re d . s p e c i a l fully nested m ode is invoked for i n t 0 and i n t 1 b y t h e s f n m b i t i n t h e in t 0 a n d in t 1 c o n t ro l re g i s t e rm , re s p e c t i v e l y , w h e n t h i s b i t i s s e t t o 1 . i n t h i s m o d e a n e w i n t e r r u p t m a y be gene rated by these sources regardless of the in-service bit. the f ollowing table shows the p r i o r i t i e s o f t h e i n t e r r upts at power-on reset. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 interrupt ty pes i n t e r r u p t n a m e interrupt t y p e vector t a b l e addres s eoi t y p e o v e r a l l priority rela ted instruc t ions d i v i d e e r r o r e x c e p t i o n (1) 0 0 h 0 0 h n / a 1 d i v , i d i v t ra c e in te rru p t (2) 0 1 h 0 4 h n / a 1 a a l l n o n - m a s k a b l e i n t e r r u p t ( n m i ) 0 2 h 0 8 h n / a 1 b b r e a k p o i n t i n t e r r u p t (1) 0 3 h 0 c h n / a 1 i n t 3 int 0 detected overflow e x c eption ( 1 ) 0 4 h 1 0 h n / a 1 i n t 0 a r r a y b o u n d s e x c e p t i o n ( 1 ) 0 5 h 1 4 h n / a 1 b o u n d u n u s e d o p c o d e e x c e p t i o n ( 1 ) 0 6 h 1 8 h n / a 1 u n d e f i n e d o p c o d e s e s c o p c o d e e x c e p t i o n ( 1 , 3 ) 0 7 h 1 c h n / a 1 e s c o p c o d e s t i m e r 0 i n t e r r u p t ( 4 , 5 ) 0 8 h 2 0 h 0 8 h 2 a t i m e r 1 i n t e r r u p t ( 4 , 5 ) 1 2 h 4 8 h 0 8 h 2 b t i m e r 2 i n t e r r u p t ( 4 , 5 ) 1 3 h 4 c h 0 8 h 2 c r e s e r v e d 0 9 h 2 4 h d m a 0 i n t e r r u p t ( 5 ) 0 a h 2 8 h 0 a h 3 d m a 1 i n t e r r u p t ( 5 ) 0 b h 2 c h 0 b h 4 i n t 0 i n t e r r u p t 0 c h 3 0 h 0 c h 5 i n t 1 i n t e r r u p t 0 d h 3 4 h 0 d h 6 i n t 2 i n t e r r u p t 0 e h 3 8 h 0 e h 7 i n t 3 i n t e r r u p t 0 f h 3 c h 0 f h 8 i n t 4 i n t e r r u p t ( 6 ) 1 0 h 4 0 h 1 0 h 9 w a t c h d o g t i m e r i n t e r r u p t ( 6 ) 1 1 h 4 4 h 1 1 h 9 a s y n c h r o n o u s s e r i a l p o r t i n t e r r u p t ( 6 ) 1 4 h 5 0 h 1 4 h 9 r e s e r v e d 1 5 h 1 f h 5 4 h 7 c h 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 interrupt ta ble n o t es if the user does not change priority l e v e l s , t h e d e f a u l t p r i o r i t y l e v e l w i l l b e u s e d f o r t h e i n t e r r u p t s o u r c e s . 1. instruction execution generates interrupts. 2. p e r f o r m e d i n t h e s a m e m a n n e r a s f o r t h e 8 0 8 6 & 8 0 8 8 . 3. an esc opc ode causes a trap. 4. only one irq is generated for the three tim e rs so t h e y s h a r e p r i o r i t y l e v e l w i t h r e g a r d t o o t h e r sources. the tim ers them selves have an interrupt priority order am ong them selves (2a > 2b > 2c). 5. these interrupt types are pr ogramm a ble in slave mode. 6. not available in slave mode. t i m e r c o n t r o l t h e i a 1 8 6 e m a n d i a 1 8 8 e m e a c h h a v e t h r e e 1 6 - b i t p r o g r a m m a b l e t i m e r s . t i m e r 0 a n d t i m e r 1 e a c h h a v e a n i n p u t a n d a n o u t p u t c o n n e c t e d t o e x t e rn a l p i n s t h a t p e rm i t t h e m t o c o u n t o r t i m e e v e n t s , p ro d u c e v a ri a b l e d u t y -c y c l e w a v e fo r m s o r n o n -re p e t i t i v e w a v e fo r m s . t i m e r1 c a n a l s o b e c o n fi g u re d a s a w a t c h d o g t i m e r. tim e r2 does not have any external connections. theref ore, it is confined to internal functions such as real-tim e coding, tim e-delay applications, a presca ler for tim er0 and tim e r1, or to synchronize dma t r a n s f e r s . the peripheral control block contains eleven 16-bit registers to cont r o l t h e p r o g r a m m a b l e t i m e r s . t h e present value of the tim er is located in the associat ed tim e r-count register, whic h m a y be read from or written to at any tim e regardless of whether the tim er is in operation or not. the value of the tim er-count re g i s t e r i s i n c re m e n t e d b y t h e m i c ro c o n t ro l l e r e v e r y t i m e a t i m e r e v e n t t a k e s p l a c e . the m a xi m u m value that each tim e r can reach is de t e r m i n e d b y t h e v a l u e s t o r e d i n t h e a s s o c i a t e d m a xi m u m c ount register. upon reaching this m a xim u m c ount value, the tim e r count register is reset to 0 i n t h e s a m e c l o c k c y c l e t h a t t h i s c ount was attained, so that the tim er count register does not store this m a xi m u m value. both tim e r0 and tim e r1 have two m a xi m u m count registers, a prim ary and a secondary r e g i s t e r , p e r m i t t i n g e a c h t i m e r t o a l t e r n a t e b e t w e e n t w o d i s c r e t e m a x i m u m v a l u e s . t i m e r 0 a n d t i m e r 1 c a n h a v e t h e m a x i m u m c o u n t r e g i s t e r s conf igured in one of two wa ys, prim ary only or b o t h p r i m a r y a n d s e c o n d a r y . i f o n l y t h e p r i m a r y i s configured to operate, on reach ing the m a ximum count the output pin will go low for one clock peri od. if both the prim ary and secondary registers are e n a b l e d , t h e o u t p u t p i n r e f l e c t s t h e s t ate of whichever of the tw o regist e r s i s i n c o n t r o l a t t h e t i m e , generating the required wavefor m that is dependent on the two values in the m a xi m u m count registers. t h e t i m e r s c a n o p e r a t e a t a q u a r t e r o f the internal clock frequency, as they are polled every fourth clock period. alternatively, an external cl ock can be used. however, in this case the tim e r output can take six clock cycles to respond to the input. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 direct memory access (dma) direct m e mory access (dma) relieves the cpu of involve ment in the transfer of data between m e mory a n d p e ri p h e ra l s o v e r e i ther one or both high-speed dma channels . data can be transferred from m e mory to i/o, i/o to m e m ory, m e mory-to-m e mory, or i/o- to-i/o. furtherm ore, the dma channels can be connected to the asynchronous serial port. the ia186em m i crocontroller supports the transfer of both bytes and words, to and from , even or odd a d d r e s s e s , b u t i t d o e s n o t s u p p o r t w o r d t r a n s f e r s t o m e m o r y t h a t i s c o n f i g u r e d f o r b y t e a c c e s s e s . t h e ia188em does not supp ort word transfers at all. each d a t a t r a n s f e r w i l l t a k e t w o bus cycles (a m i nim u m of 8 clock cycles). t h e re a re t h re e s o u rc e s o f d m a re q u e s t s fo r each dma channel: the channel request pin ( drq1 ? drq0 ) , t i m e r2 , o r t h e s y s t e m s o ft w a re . t h e t w o c h a n n e l s can be programm ed to have different priorities to f a c i l i t a t e t h e r e s o l u t i o n o f s i m u l t a n e o u s d m a r e q u e s t s o r t o i n t e r r u p t a t r a n s f e r o n t h e o t h e r c h a n n e l . dma op eration the peripheral control block contai n s s i x re g i s t e rs fo r e a c h d m a c h a n n e l t o c o n t ro l a n d s p e c i fy t h e operation of the channels. the six regi sters consist of a pair of register s to store a 20-bit source address, a pair of registers to store a 20-bit destination address, a 16-bit transfer count register, and a 16-bit control r e g i s t e r . the num ber of dma transfers required is designated in the dma transfer count register and can be up to 64k bytes or words and, furtherm ore, will end au tom a tically. dma channel function is defined by the control registers, which along with the other 5 registers can be cha nged at any tim e, including during a dma transfer and are implem e nted imm e diately. dma channel cont rol regist ers s e e d 1 c o n ( 0 d a h ) & d0con (0cah) - d m a c o n t ro l re g i s t e rs a b o v e . bri e fly, these reg i sters specify t h e f o l l o w i n g : " i s t h e d a t a d e s t i n a t i o n i n m e m ory or i/o space? (bit 15). " i s t h e d e s t i n a t i o n a d d r e s s i n c r e m e n t e d , d e c r e m e n t e d , o r u n c h a n g e d a ft e r e a c h transfer? (bit 14 & 13). " is the data source in m e mo ry o r i/ o s p a c e ? (bi t 1 2 ). " i s t h e s o u r c e a d d r e s s i n c r e m e n t e d , d e c r e m e n t e d , o r u n c h a n g e d a f t e r e a c h t r ansfer? (bit 11 & 10). " do dma transfers cease upon reach i ng a designated count? (bit 9). " does the las t transfer gene rate an interrupt? (bit 8). " synchronization m ode. (bits 7 & 6). " t h e r e l a t i v e p r i o r i t y o f o n e d m a c h a n n e l w i t h r e s p e c t t o t h e o t h e r . ( b i t 5 ) . " a c c e p t a n c e o f d m a r e q u e s t s f r o m t i m e r 2 . ( b i t 4 ) . " byte or word transfers. (bit 0). 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m f i g u r e 4 . d m a u n i t dma priority dma transfers have a higher prio rity than cpu tran s f e r s , w i t h t h e e x c e p t i o n o f w o r d a c c e s s e s t o o d d m e mory locations o r between locked m e m ory addresses. th e cpu cannot access m e mory during a dma transfer and a dma tran sfer cannot be suspended by an interrupt re qu est. continuous dma activity will thus cause interrupt latency to suffer. however, a n n m i r e q u e s t h a l t s a n y d m a a c t i v i t y , e n a b l i n g t h e cpu to respond prom ptly to the request. 20 - bit a dder/subtractor adder control l o g i c transfer counter ch. 1 d e s t i n a t i o n a d d r e s s c h . 1 source address c h. 1 transfer counter ch. 0 d e s t i n a t i o n a d d r e s s c h . 0 source addr e s s c h . 0 d m a c o n t r o l l o g i c 20 re q u e s t selection l o g i c i n t e r r u p t re q u e s t t i m e r r e q u e s t channel c ontrol r egister 1 channel c ontrol r egister 0 20 16 in t e rn a l a d d r e s s / d a t a bu s drq1 drq0
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a s y n c h r o n o u s s e r i a l p o r t the asynchronous serial port em ploys s t a n d a rd i n d u s t ry c o m m u n i c a t i o n p r o t o c o l s i n i t s i m p l e m e n t a t i o n of full duplex, bi-directional data transfers. the port can be the source or destination of dma transfers. the following features are supported: " full-duplex data transfers " 7-, 8-, or 9-bit data transfers " odd, even, or no parity " one or two stop bits " error detection provided by parit y, fram ing, or overrun errors " hardware handshaking is achieved with the follow i n g s e l e c t a b l e c o n t r o l s i g n a l s : c l e a r - t o - s e n d ( c t s _ n ) o e n a b l e r e c e i v e r r e q u e s t ( enrx_n ) o ready to send ( r t s _ n ) o re a d y t o re c e i v e ( r t r _ n ) " d m a t o a n d f r o m t h e p o r t " the port has its own m a s kable interrupt " the port has an independent baud rate generator " maxim u m baud rate is 1/32 of the processor clock " t ra n s m i t a n d re c e i v e l i n e s a re d o u b l e b u ffe re d in power-save m ode the baud rate generator divide f a c t o r m u s t b e re -p ro g ra m m e d t o c o m p e n s a t e fo r t h e change in clock rate. s y n c h r o n o u s s e r i a l p o r t the synchronous serial port allows the m i crocontrolle rs to communicate with asic s that are required to b e p ro g ra m m e d b u t h a v e a p i n s h o rt a g e . t h e fo u r-p in interface allows h a lf- duplex, b i -directional data t r a n s f e r a t a m a x i m u m o f 2 0 m b i t s /sec with a 40 mhz cpu c l ock. the synchro nous serial interface of the ai186em/ai188e m o p e r a t e s a s t h e m a s t e r p o r t i n a m a s t e r / s l a v e a r r a n g e m e n t . t h e r e a r e f o u r p i n s i n t h e s y n c h r o n o u s s e r i a l i n t e r f a c e f o r c o m m u n i c a t i o n w i t h t h e s y s t e m e l e m e n t s . these pins are two enab les (sden0 and sden 1), a clock (s clk) and a data pin (sdata). in power-save m ode, the baud rate generator divide f a c t o r m u s t b e re -p ro g ra m m e d t o c o m p e n s a t e fo r t h e change in clock rate. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 progra mmable i/o (pio) 3 2 p i n s a re p ro g ra m m a b l e a s i/ o s i g n a l s . t h e f o l l o w i n g t a b l e s l i s t t h e s e pins with their pin nam e and pio n u m b e r , f i r s t i n p i o n u m e r i c a l o r d e r, then in pin nam e alphabetical order. programmi ng a pin as a pio should only be perform e d if the norm a l pin func tion is not required as the norm a l func tion is disabled and no longer has any affect on the pin. a pio pin can be programmed as an input or output with or without either a weak pull-up or pull-down, or as an open-drain output. followi ng a power-on reset, the pio pins have default status as sh own in the following tables. p i o no. associated pin p o w e r - o n r e s e t status associated pin p i o n o . p o w e r - o n r e s e t status 0 t m r i n 1 i n p u t w i t h p u l l - u p a 1 7 7 n o r m a l o p e r a t i o n ( 3 ) 1 t m r o u t 1 i n p u t w i t h p u l l - d o w n a 1 8 8 n o r m a l o p e r a t i o n ( 3 ) 2 p c s 6 _ n / a 2 i n p u t w i t h p u l l - u p a 1 9 9 n o r m a l o p e r a t i o n ( 3 ) 3 p c s 5 _ n / a 1 n o r m a l o p e r a t i o n ( 3 ) d e n _ n / d s _ n 5 n o r m a l o p e r a t i o n ( 3 ) 4 dt/r_n n o r m a l o p e r a t i o n ( 3 ) d r q 0 1 2 i n p u t w i t h p u l l - u p 5 d e n _ n n o r m a l o p e r a t i o n ( 3 ) d r q 1 1 3 i n p u t w i t h p u l l - u p 6 s r d y n o r m a l o p e r a t i o n ( 3 ) dt/r_n 4 n o r m a l o p e r a t i o n ( 3 ) 7 ( 1 ) a 1 7 n o r m a l o p e r a t i o n ( 3 ) in t2/ 3 1 i n p u t w i t h p u l l - u p 8 ( 1 ) a 1 8 n o r m a l o p e r a t i o n ( 3 ) i n t 4 3 0 i n p u t w i t h p u l l - u p 9 ( 1 ) a 1 9 n o r m a l o p e r a t i o n ( 3 ) m c s 0 _ n 1 4 i n p u t w i t h p u l l - u p 1 0 t m r o u t 0 i n p u t w i t h p u l l - d o w n m c s 1 _ n 1 5 i n p u t w i t h p u l l - u p 1 1 t m r i n 0 i n p u t w i t h p u l l - u p m c s 2 _ n 2 4 i n p u t w i t h p u l l - u p 1 2 d r q 0 i n p u t w i t h p u l l - u p m c s 3 _ n / r f s h _ n 2 5 i n p u t w i t h p u l l - u p 1 3 d r q 1 i n p u t w i t h p u l l - u p p c s 0 _ n 1 6 i n p u t w i t h p u l l - u p 1 4 m c s 0 _ n i n p u t w i t h p u l l - u p p c s 1 _ n 1 7 i n p u t w i t h p u l l - u p 1 5 m c s 1 _ n i n p u t w i t h p u l l - u p p c s 2 _ n 1 8 i n p u t w i t h p u l l - u p 1 6 p c s 0 _ n i n p u t w i t h p u l l - u p p c s 3 _ n 1 9 i n p u t w i t h p u l l - u p 1 7 p c s 1 _ n i n p u t w i t h p u l l - u p p c s 5 _ n / a 1 3 i n p u t w i t h p u l l - u p 1 8 p c s 2 _ n i n p u t w i t h p u l l - u p p c s 6 _ n / a 2 2 i n p u t w i t h p u l l - u p 1 9 p c s 3 _ n i n p u t w i t h p u l l - u p r x d 2 8 i n p u t w i t h p u l l - u p 2 0 s c l k i n p u t w i t h p u l l - u p s 6 / c l k d i v 2 2 9 i n p u t w i t h p u l l - u p ( 1 , 2 ) 2 1 s d a t a i n p u t w i t h p u l l - u p s c l k 2 0 i n p u t w i t h p u l l - u p 2 2 s d e n 0 i n p u t w i t h p u l l - u p s d a t a 2 1 i n p u t w i t h p u l l - u p 2 3 s d e n 1 i n p u t w i t h p u l l - u p s d e n 0 2 2 i n p u t w i t h p u l l - u p 2 4 m c s 2 _ n i n p u t w i t h p u l l - u p s d e n 1 2 3 i n p u t w i t h p u l l - u p 2 5 m c s 3 _ n / r f s h _ n i n p u t w i t h p u l l - u p s r d y 6 n o r m a l o p e r a t i o n ( 4 ) 2 6 ( 1 , 2 ) u z i _ n i n p u t w i t h p u l l - u p t m r i n 0 1 1 i n p u t w i t h p u l l - u p 2 7 t x d i n p u t w i t h p u l l - u p t m r i n 1 0 i n p u t w i t h p u l l - u p 2 8 r x d i n p u t w i t h p u l l - u p t m r o u t 0 1 0 i n p u t w i t h p u l l - d o w n 2 9 ( 1 , 2 ) s 6 / c l k d i v 2 i n p u t w i t h p u l l - u p t m r o u t 1 1 i n p u t w i t h p u l l - d o w n 3 0 i n t 4 i n p u t w i t h p u l l - u p t x d 2 7 i n p u t w i t h p u l l - u p 3 1 i n t 2 i n p u t w i t h p u l l - u p u z i _ n 2 6 i n p u t w i t h p u l l - u p n o t e s these notes apply to both tables: 1. e m u l a t o r s u s e t h e s e p i n s a n d a l s o s2_n-s0_n, res_n, nmi, clkouta, bhe_n ale, ad15-ad0, and a15-a0 . 2. if bhe_n/aden_n (ia186em) or r f s h _ n / a d e n _ n (ia188m) is held low during power-on reset, these p i n s w i l l r e v e r t t o n o r m a l o p e r a t i o n . 3. input with pull-up option available when used as pio. 4. input with pull-down option available when used as pio. these default status setting m a y be changed as desired. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 t h e t h r e e m o s t s i g n i f i c a n t bits of the address bus ( a19 ?a17 ) start with their norm a l function on power- o n r e s e t , p e r m i t t i n g t h e p r o c e s s o r t o b e g i n f e t c h i n g i n s t r u c t i o n s f r o m t h e b o o t a d d r e s s f f f f 0 h . f u r t h e r m o r e , n o r m a l f u n c t i o n i s t h e d e f a u l t s e t t i n g f o r d t / r _ n , den_n , and srdy on power-on reset. s6/clkdiv2_n and u z i _ n a u t o m a t i c a l l y r e t u r n t o n o r m a l o p e r a t i o n i n t h e e v e n t t h a t t h e ad15-ad0 bus override is enabled. the ad15-ad0 bus override is enabled if the b h e _ n / a d e n _ n fo r t h e ia 1 8 6 e m , o r t h e rfsh2_n/aden_n for the ia188em, is held low during power-on reset. p i n d e s c r i p t i o n s a19 (pio9), a18 (pio8), a17 (pio7), a16 ?a0 address bus (synchronous outputs w i th tristate) t h e s e p i n s a r e t h e s y s t e m s s o u r c e o f n o n - m u l t i p l e xed i/o or m e mory addresses and o c cur a half c l k o u t a c y c l e b e f o r e t h e m u l t i p l e x e d a d d r e s s / d a t a b u s ( ad 15-ad0 for the ia186em or a o 1 5 _ a o 8 and ad7-ad0 for the ai188em). the address bus is tristated during a bus hold or reset. ad15 ?ad8 ia 186e m a d d r e s s / d a ta b u s (l e v e l -s e n s i ti v e s y n c h r o n o u s i n o u ts w i th tr i s ta te ) t h e s e p i n s a r e t h e s y s t e m s s o u r c e o f t i m e - m u l t i p l e x e d i / o o r m e m o r y a d d r e s s e s a n d d a t a . t h e a d d r e s s function of these pins can be disabled. (see bhe_n/aden_n pin description.) if the address function of these pins is enabled, the address wi ll be present on this bus during t 1 of the bus cycle and data will be present during t 2 , t 3 , a n d t 4 of the sam e bus cycle. if w h b _ n is not active, these pins are tristated during t 2 , t 3 , a n d t 4 o f t h e b u s c y c l e . the address/data bus is trista ted during a bus hold or reset. these pins can be used to load the internal reset configuration register (res con, offset 0f6h) with configuration data dur ing a power-on reset. ad7 ?ad0 a d d r e s s / d a ta b u s (l e v e l -s e n s i ti v e s y n c h r o n o u s i n o u ts w i th tr i s ta te ) t h e s e p i n s a r e t h e s y s t e m s s o u r c e o f t i m e - m u l t i p l e x e d l o w - o r d e r b y t e o f t h e a d d r e s s e s f o r i / o o r m e m o r y and 8-bit data. the low-order address byt e will be present on this bus during t 1 o f t h e b u s c y c l e a n d t h e 8 - bit data will be present during t 2 , t 3 , a n d t 4 of the sam e bus cycle. the address function of these pins can be disabled. (see bhe_n/aden_n pin description.) if w l b _ n is not active, these pins are tristated during t 2 , t 3 , a n d t 4 of the bus cycle. t he address/data bus is tristated during a bus hold or reset. ao15 ?ao8 ia 188e m a d d r e s s -o n l y b u s (l e v e l -s e n s i ti v e s y n c h r o n o u s o u tp u ts w i th tr i s ta te ) the address-only bus will contain valid high-o rder address bits during the bus cycle (t 1 , t 2 , t 3 , and t 4 ) i f t h e bus is enabled. t h e s e p i n s a re c o m b i n e d w i t h a d 7 - a d 0 t o c o m p l e t e t h e m u l t i p l e x e d a d d r e s s b u s a n d a r e t r i s t a t e d d u r i n g a bus hold or reset condition. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 ale address latch ena b le (synchronous output) this signal indicates the presence of an address on the address bus ( a d 1 5 - a d 0 for the ia186em or ao15- ao8 and ad7-ad0 for the ai188em), which is guaranteed to b e valid on th e falling edg e of a l e . ardy asynchronous ready (level-sensitive asynchronous input) this asynchronous signal provides an i n d i c a t i o n t o t h e m i c r o c o n t r o l l e r t h at the addressed i/o device or m e m o ry s p a c e w i l l c o m p l e t e a d a t a t ra n s fe r. t h i s a c t i v e h i g h s i g n a l i s a s y n c h r o n o u s w i t h r e s p e c t t o c l k o u t a a n d i f t h e f a l l i n g e d g e o f ardy is not synchronized to c l k o u t a and additional clock cycle m a y be added ardy s h o u l d b e t i e d h i g h t o m a i n t a i n a p e r m a n e n t a s s e rtion of the ready conditi on. o n the other h a nd, if t h e ardy signal is not used by the system it shoul d b e t i e d l o w , w h i c h p a s s e s c o n t ro l t o t h e s r d y s i g n a l . bhe_n/aden_n ia186em o n l y bus high enable (synchron ous out put w i th tristate) /address enable (input w i th internal pull-up) bhe_n - bhe_n and address b i t a d 0 o r a0 inform the system which bytes of the data bus (upper, lower, or b o t h ) a r e i n v o l v e d i n t h e c u r r e n t m e m o r y a c c e s s b us cycle as s hown in the following table. bhe_n ad0 type of bus cycle 0 0 word transfer 0 1 high-byte t r ansfer (bits 15-8) 1 0 low-byte transfer (bits 7-0) 1 1 refresh bhe_n d o e s n o t r e q u i r e l a t c hing and during bus hold a n d re s e t i s t r i s t a t e d . it is asserted during t 1 a n d rem a ins so through t 3 a n d t w . the high and low byte write enable functions of bhe_n and a d 0 a r e p e r f o r m e d b y w h b _ n and w l b _ n r e s p e c t i v e l y . when using the ad bus, dram refr esh cycles are indicated by bhe_n/aden_n and ad0 both being high. during refresh cycles the a and ad busses m a y not have the sam e addr ess during the address phase of the ad bus cycle necessitating the use of a d 0 a s a d e t e r m i n a n t f o r t h e r e f r e s h c y c l e r a t h e r t h a n a 0 . a n a d d i t i o n a l s i g n a l i s u t i l i z e d f o r p s r a m r e f r e s h e s ( s e e m c s 3 _ n / r f s h _ n pin description). aden_n t h e re i s a w e a k i n t e rn a l p u l l -u p o n b h e_n/aden_n obviating the need for an e x t e rn a l p u l l -u p a n d re d u c i n g power consumption. holding aden_n high or letting it float duri ng power-on reset passes control of the address function of the ad bus ( ad15-ad0 ) during lcs and ucs bus cycles from aden_n t o t h e d a b i t i n lmcs and umcs r e g i s t e r s . w h e n t h e a d d r e s s f u n c t i o n i s s e lected, the m e mory address is placed on the a19-a0 p i n s . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 holding aden_n low during power-on reset, both the a ddress and data are driven onto the ad bus independently of the da bit setting. this pin is norm ally sampled one clock cycle after the rising edge of r e s _ n . clkou t a ? clock outpu t a (synchronous output) this pin is the internal clock output to the system. bits 9, 8, and 2-0 of the p o w e r - s a v e c o n t r o l r e g i s t e r ( p d c o n ) c o n t r o l t h e o u t p u t of this pin, which may be tristated, out put the crystal inpu t fre q u e n c y (x 1 ), or output the power save fr e q u e n c y (i n t e rn a l p ro c e s s o r frequency after divisor). c l k o u t a can be used as a full speed clock source in power-save m ode. the a.c. t i m i n g s p e c i f i c a t i o n s t h a t a r e c l o c k -re l a t e d re fe r t o c l k o u t a , which rem a ins active during reset and hold conditions. clkou t b ? clock outpu t b (synchronous output) this pin is an additional clock out put to the system . bits 11, 10, and 2-0 of the power-save control register (pdcon) control the output of this pin, which m a y be tris tated, output the pll frequency, or m a y output the power save frequency (inter nal processor frequency after divisor). c l k o u t b r e m a i n s a c t i v e during reset and hold conditions. den_n (pio5) ?data enable strobe ( synchronous output with tr ista te) this pin pro vides an ou tput enable to an exte rna l b u s d a t a b u s t r a n s m i t t e r o r r e c e i v e r . t h i s s i g n a l i s a s s e r t e d during i/o, m e mory, and interrupt acknowle dge processes and is deasserted when d t / r _ n undergoes a change of state. it is tr istated for a bus hold or reset. drq1-drq (pio12-pio13) ?dma requests (synchronous level-sensitive inputs) drq0 ? an external device that is ready for dma channel 1 or 0 to carry out a transfer indicates to the m i c ro c o n t ro l l e r t h i s re a d i n e s s o n t h ese pins. they are level trigge red, internally synchronized, not latched, and must rem a in asserted until dealt with. dt/r_n (pio4 ) ?data transmit or r eceive (synchronous output w i th tristate) t h e m i c r o n t r o l l e r t r a n s m i t s d a t a w h e n d t / r _ n is pulled high and receives data when this pin is pulled low. it floats during a reset or bus hold condition. gnd ?ground six or seven pins, depending on package, c onnect the m i crocontrolle r t o t h e s y s t e m g r o u n d . hlda ?bus hold acknow ledge (synchronous output) this pin is pulled high to signal the system that the m i c r o n t r o l l e r h a s c e d e d c o n t r o l o f t h e l o c a l b u s , i n response to a high on the h o l d signal by an external bus m a ster, af t e r t h e m i c r o c o n t r o l l e r h a s c o m p l e t e d t h e c u r r e n t b u s c y c l e . t h e a s s e r t i o n o f hlda is accom panied by the tristating of den_n, rd_n, w r _n, s2_n-s0_n, ad15-ad0, s6, a19-a0, bhe_n, w hb_n, w l b_n, and d t / r _ n , followed by the driving high of the chip selects ucs_n, lcs_n , mcs3_n - mcs0_n, pcs6_n ? pcs5_n, and pcs3_n ?pcs0_n . the external bus m a ster releases control of the local bus by the deassertion of h o l d that in turn induces the m i crocontroller to deassert the hlda . the m i crocontroller can take control of th e bus if necessary (to execute a refresh for exam ple), by deasserting hlda w i t h o u t t h e b u s m a s t e r f i r s t d e a s s e r t i n g h o l d . this requires that the external bus m a ster be able to deassert h o l d t o p e r m i t t h e m i c r o c o n t r o l l e r t o a c c e s s t h e b u s . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 h o l d b u s h o l d r e q u e s t ( s y n c h r o n o u s l e v e l - s e n s i t i v e i n p u t ) this pin is pulled high to signal th e m i c r o c o n t r o l l e r t h a t t h e s y s t e m r e quires control of the local bus. h o l d l a t e n c y t i m e ( t i m e b e t w e e n t h e h o l d and hlda ) depends on the current pr o c e s s o r a c t i v i t y w h e n t h e h o l d is received. a hold request is second only do a dma refresh request in priority of pr ocessor activity requests. if a hold re q u e s t i s re c e i v e d a t t h e m o m e n t a d m a t r a n s f e r s t a r t s , t h e h o l d latency can be up to 4 b u s c y c l e s . (o n t h e ia 1 8 6 e m o n l y , t h i s happens when a word transfer is t a k i n g p l a c e fro m a n o d d t o a n odd address). this m eans that the latency m a y be 16 clock cycles without wait st a t e s . f u rt h e rm o re , i f lock transfers are being perform e d, then the latency tim e i s i n c re a s e d b y t h e d u ri n g of the locked transfer. int0 ?maskable interrupt request 0 (asynchronous input) the i n t 0 pin provides an indication th at an interrupt request has occurred, and provided that i n t 0 is not m a s k e d , p r o g r a m e x e c u t i o n w i l l c o n t i n u e a t t h e l o c a t i o n s p e c i f i e d b y t h e i n t 0 v e c t o r i n t h e i n t e r r u p t vector table. although interrupt requests are asynchronous, they are synchronized internally and m a y be e d g e - o r l e v e l - t r i g g e r e d . t h e a s s e r t i o n o f t h e i n t e r r u p t r e q u e s t m u s t b e m a i n t a i n e d u n t i l i t i s h a n d l e d , t o ensure that it is recognized. int1/select_n ?maskable interrupt request 1/ slave select (both are asynchronous inputs) i n t 1 - the int1 pin provides an indication that an inte rrupt request has occu rre d , a n d p ro v i d e d t h a t i n t 1 i s n o t m a s k e d , p ro g ra m e x e c u t i o n w i l l c o n t i n u e a t t h e l o c a tion specified by the int1 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and m a y be e d g e - o r l e v e l - t r i g g e r e d . t h e a s s e r t i o n o f t h e i n t e r r u p t r e q u e s t m u s t b e m a i n t a i n e d u n t i l i t i s h a n d l e d , t o ensure that it is recognized. select_n this pin provides an indication to the m i crocont roller that an interrupt type has been placed on the address/data bus when th e i n t e r n a l i n t e r r u p t c o n t r o l u n i t i s s l a v e d t o a n e x t e r n a l i n t e r r u p t c o n t r o l l e r . before this occurs, how ever, the i n t 0 pin m ust have indicated an interrupt request has occurred. int2/in ta0_ n (pio31) ? maskable interrupt request 2 (a s y n c h r o n o u s i n p u t) / i n te r r u p t a c k n o w l e d g e 0 (synchronous output) i n t 2 - the int2 pin provides an indication that an inte rrupt request has occu rre d , a n d p ro v i d e d t h a t i n t 2 i s n o t m a s k e d , p ro g ra m e x e c u t i o n w i l l c o n t i n u e a t t h e l o c a t i o n s p e c i f i e d b y t h e i n t 2 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and m a y be e d g e - o r l e v e l - t r i g g e r e d . t h e a s s e r t i o n o f t h e i n t e r r u p t r e q u e s t m u s t b e m a i n t a i n e d u n t i l i t i s h a n d l e d , t o ensure that it is recognized. w hen i n t 0 is configured to be in cascade m ode, i n t 2 changes its function to inta0_n . inta0_n ? this function indicates to the s y s t e m t h a t t h e m i c r o c o n t r o l l e r requires an interrupt type in response to the interrupt request i n t 0 when the m i crocontroller? interr upt control unit is in cascade m o d e . t h e p e ri p h e ra l d e v i c e t h a t i s s u e d t h e i n t e r r u p t m u s t p r o v i d e t h e i n t e r r u p t t y p e . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i nt3/inta1_n/irq ?maskable in terrupt request 3 (asynchronous input) / interrupt acknow ledge 1 (synchronous output) / interrupt acknow ledge (synchronous output) i n t 3 - the int3 pin provides an indication that an inte rrupt request has occu rre d , a n d p ro v i d e d t h a t i n t 3 i s n o t m a s k e d , p ro g ra m e x e c u t i o n w i l l c o n t i nue at the location specified by the i n t 3 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and m a y be e d g e - o r l e v e l - t r i g g e r e d . t h e a s s e r t i o n o f t h e i n t e r r u p t r e q u e s t m u s t b e m a i n t a i n e d u n t i l i t i s h a n d l e d , t o ensure that it is recognized. w hen i n t 1 is configured to be in cascade m ode, i n t 3 changes its function to inta1_n . inta1_n ? this function indicates to the s y s t e m t h a t t h e m i c r o c o n t r o l l e r requires an interrupt type in response to the interrupt request i n t 1 when the m i crocontroller? interr upt control unit is in cascade m o d e . t h e p e ri p h e ra l d e v i c e t h a t i s s u e d t h e i n t e r r u p t m u s t p r o v i d e t h e i n t e r r u p t t y p e . irq ? w i t h t h e i n t e r r u p t c o n t r o l u n i t o f t h e m i c r o c o n t r o ller in slave m ode, the signal on this pin allows the m i crocontroller to output an i n t e r r u p t r e q u e s t t o t h e e x t e r n a l m a s t e r i n t e r r u p t c o n t r o l l e r . int4/pio30 ?maskable interrupt request 4 (asynchronous input) i n t 4 - the int4 pin provides an indication that an inte rrupt request has occu rre d , a n d p ro v i d e d t h a t i n t 4 i s n o t m a s k e d , p ro g ra m e x e c u t i o n w i l l c o n t i nue at the location specified by the i n t 4 vector in the interrupt vector table. although interrupt requests are asynchronous, they are synchronized internally and m a y be e d g e - o r l e v e l - t r i g g e r e d . t h e a s s e r t i o n o f t h e i n t e r r u p t r e q u e s t m u s t b e m a i n t a i n e d u n t i l i t i s h a n d l e d , t o ensure that it is recognized. l c s _ n / o n c e 0 _ n l o w e r m e m o r y c h i p select (synchronous output w i th internal p u ll-up) / once mode request (input) l c s _ n - the lcs_n p i n p ro v i d e s a n i n d i c a t i o n t h a t a m e m o ry a c c e s s i s o c c u r r i n g t o t h e l o w e r m e m o r y b l o c k . t h e s i z e o f t h e l o w e r m e m o ry bl o c k a n d i t s base address are programm able, with the size adjustable up to 512 kbytes. lcs_n is held high during bus hold. once0_n ?(onc e ? o n c i r c u i t e mulation). this pin and its com p anion pin once1_n define the m i c r o c o n t r o l l e r m o d e d u r i n g r e s e t . t h e s e t w o pins are sam pled on the rising edge of r e s _ n and if both a re a s s e rt e d l o w t h e m i c ro c o n t ro l l e r s t a rt s i n o n ce m o d e , e l s e i t s t a rt s n o rm a l l y . in o n ce m o d e , a l l p i n s a r e t r i s t a t e d a n d r e m a i n s o u n t i l a s u b s e q u e n t r e s e t . t o p r e v e n t t h e m i c r o c o n t r o l l e r f r o m e n t e r i n g o n c e m o d e i n a d v e r t e n t l y , t h i s pin has a weak pull-up that is only pres ent during reset. finally, this pin is not tristated during bus hold. mcs2_n ?mcs0_n (no pio - pio15 ?pio 14) ?midran ge memory chip selects (syn chronous outputs w i th i n te r n a l p u l l -u p ) m c s 0 _ n - t h e m c s 2 _ n a n d m c s 0 _ n p i n s p r o v i d e a n i n d i c a t i o n t h a t a m e m o r y a c c e s s i s i n t r a i n t o e i t h e r the second or third m i drange m e mory block. the size of the midrange mem o ry bloc k and its base a d d r e s s a r e p r o g r a m m a b l e . mcs2_n ? mcs0_n are held high during bus hold and have weak pull-ups that are only present during reset. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 mcs3_n/rfsh_n (pio25) ? midrange memory c h ip select (synchronous o u t p u t w i t h i n t e r n a l p u l l - u p ) / automatic refresh (sy n chronous output) m c s 3 _ n - t h e m c s 3 _ n p i n p r o v i d e s a n i n d i c a t i o n t h a t a m e m o r y access is in train to the fourth region of the m i drange m e mory block. the size of the mi drange mem ory block and its base address are p r o g r a m m a b l e . m c s 3 _ n is held high during bus hold and has a weak pull-up that is present only during r e s e t . r fs h _ n ?this signal is tim e d for auto refresh to p s ra m o r d ra m d e v i c e s . t h e refresh pulse is output only when the psram or dram mode bit is set (edram register bit 15 ). this pulse is of 1.5 clock pulse duration with the rest of th e refresh cycle made up of a deasse rtion period such that the overall r e f r e s h t i m e i s m e t . f i n a l l y , t h i s pin is not tristated during a bus hold. nmi ?nonmaskable interrupt (synchronous edge-sensitive input) this is the highest priority interru pt signal and cannot be m a sked, unlike int4 ?int0 . p r o g r a m e x e c u t i o n i s t r a n s f e r r e d t o t h e n o n m a s k a b l e i n terrupt vector in the in terrupt vector table, upon the assertion of this interrupt (transition from low to high), and this interrupt i s i n i t i a t e d a t t h e n e x t instruction boundary. for rec ognition to be assured the n m i p i n m u s t b e h e l d h i g h fo r a t l e a s t a clkouta p e r i o d s o t h a t t h e t r a n s i t i o n f r o m l o w t o h i g h i s l a t c h e d a n d s y n c h r o n i z e d i n t e r n a l l y . t h e i n t e r r u p t w i l l b e g i n a t t h e n e x t i n struction boundary. the n m i is not involved in the priority resolution process that deals wi th the m a skable interrupts, and does not have an associated interrupt flag. this allo w s f o r a n e w n m i r e q u e s t t o i n t e r r u p t a n n m i s e r v i c e routine that is already underway. th e i n t e r r u p t f l a g i f i s c l e a r e d , d i s a b l i n g t h e m a s k a b l e i n t e r r u p t s , w h e n an interrupt is taken by the processor. if, during th e n m i s e r v i c e r o u t i n e , t h e m a s k a b l e i n t e r r u p t s a r e r e - enabled, by use of sti instruction fo r e x a m p l e , t h e p r i o r i t y r e s o l u t i o n of m a skable interrupts will be unaffected by the servicing of the nm i. for this reason, it is strongly recomm ended that the nmi interrupt s e r v i c e r o u t i n e d o e s n o t e n a b l e t h e m a s k a b l e i n t e r r u p t s . pcs3_n - pcs0_n (pio19 ? pio16) ? peripheral c h ip selects 3-0 (synchronous outputs) these pins p r ovide an in dication that a m e mory access is und er way for the correspo nding reg i on of the p e ri p h e ra l m e m o ry b l o c k (i/ o o r m e m o ry a d d re s s s p a c e ). t h e b a s e a d d r e s s o f t h e p e ri p h e ra l m e m o ry block is programm able. pcs3_n ?pcs0_n are held high during both bus hold and reset. these outputs are asserted with the ad address bus over a 256-byte range each. pcs5_n/a1? peripheral chip select 5 (synchronous output) / latched address bit 1 (synchronous o u t p u t ) pcs5_n t h i s s i g n a l p r o v i d e s a n i n d i c a t i o n t h a t a m e m o r y a c c e s s i s u n d e r way for the sixth region of the p e ri p h e ra l m e m o ry b l o c k (i/ o o r m e m o ry a d d re s s s p a c e ). t h e b a s e a d d r e s s o f t h e p e ri p h e ra l m e m o ry block is programm able. pcs5_n is held high during both bus hold and rese t. this output is asserted with t h e ad a d d re s s b u s o v e r a 2 5 6 -b y t e ra n g e . a1 ? this pin provides and internally latched address bit 1 t o t h e s y s t e m w h e n t h e e x b i t ( b i t 7 ) i n t h e mcs_n and pcs_n auxiliary ( mpcs) registe r is 0. it r e t a i n s i t s p r e v i o u s l y l a t c h e d v a l u e d u r i n g a b u s hold. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 pcs6_n/a2/ ?peripheral chip sele ct 6 (synchronous output) / latc hed address bit 2 (synchronous o u t p u t ) pcs6_n t h i s s i g n a l p r o v i d e s a n i n d i c a t i o n t h a t a m e m o r y a c c e s s i s u n d e r way for the seventh region of t h e p e ri p h e ra l m e m o ry b l o c k (i/ o o r m e m o ry a d d re s s s p a c e ) . t h e b a s e a d d r e s s of the peripheral m e mory block is programm able. pcs6_n is held high during both bus hold and rese t. this output is asserted with t h e ad a d d re s s b u s o v e r a 2 5 6 -b y t e ra n g e . a2 ? this pin provides and internally latched address bit 2 t o t h e s y s t e m w h e n t h e e x b i t ( b i t 7 ) i n t h e mcs_n and pcs_n auxiliary ( mpcs) registe r is 0. it r e t a i n s i t s p r e v i o u s l y l a t c h e d v a l u e d u r i n g a b u s hold. pio31 ?pio0 programmable i/o pins (asynchronous input/output open ?rain) 32 individually programm able i/o pins are provided. see page 62. r d _ n - r e a d s tr o b e (s y n c h r o n o u s o u tp u t w i th tr i s ta te ) this pin provides an indication to th e system that a m e mory or i/o read cycle is under way. it will not to be asserted before the a d bus is floated during the a ddress to data transition. rd_n is tristated during bus hold. r e s _ n - r e s e t ( a s y n c h r o n o u s l e v e l - s e n s i t i v e i n p u t ) t h i s p i n f o r c e s a r e s e t o n t h e m i c r o c o n t r o l l e r . i t h a s a s c h m i t t t r i g g e r t o a l l o w p o w e r - o n r e s e t g e n e r a t i o n via an rc network. w h en this signal is asserted, th e m i c r o c o n t r o l l e r i m m e d i a t e l y t e r m i n a t e s i t s p r e s e n t activity, clears its internal logic, and transfer s cpu control to the reset address, ffff0h. r e s _ n m ust be asserted f or at least 1m s and m a y be asserted asynchronously to c l k o u t a a s i t i s synchronized internally. furtherm ore, v cc m u s t b e w i t h i n s p e c i fi c a t i o n and clkouta must be stable for more than four of its clock periods for the period that r e s _ n i s a s s e r t e d . t h e m i c ro c o n t ro l l e r s t a rt s to fetch instructions 6.5 c l k o u t a clock periods after the deassertion of res_n . rfsh2_n/aden_n - ia 188e m o n l y - refresh 2 (synchronous output w i t h t r i s t a t e ) / a d d r e s s e n a b l e (input w i th internal pull-up) rfsh2_n ?indicates that a dram refresh cycle is being perf orm e d when i t is asserted low. howe ver, this is not valid in psram mode where m c s 3 _ n / r f s h _ n is used instead. aden_n if t h i s p i n i s h e l d h i gh during power-on reset, the a d bus ( ao15-ao8 & ad7-ad0 ) i s c o n t ro l l e d during the address portion of the lc s and ucs bus cycles by the da bit (bit 7) in the lcs and ucs regis t ers. if the da bit is 1, the address is access e d on the a19-a0 pins reducing power consum ption. the weak pull-u p on this p i n obviates the necessity of an external pull-up. if this pin is held low during power-o n reset, the ad bus is used for bot h addresses and data without regard f o r t h e s e t t i n g o f t h e d a b i t s . rfsh2_n/aden_n i s s a m p l e d o n e c ry s t a l c l o c k c y cle after the rising edge of r e s _ n and is tristated during bus holds and once m ode. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 rxd (pio28) - receive d ata (asynch r onous input) this signal connects asynchronous serial receive data from the system to the asynchronous serial port. s 2 _ n -s 0 _ n - bu s c y c l e s ta tu s (s y n c h r o n o u s o u tp u ts w i th tr i s ta te ) these three signals inform the system of the type of bus cycle is in progress. s2_n may be used to indicate whether the current acce ss is to m e m ory or i/o, and s 1 _ n m a y be used to indicate whether data is b e i n g t r a n s m i t t e d o r r e c e i v e d . t h e s e s i g n a l s a r e tris tated during bus hold and hold acknowledge. the coding for these pins is shown in the following table. s2_n s1_n s0_n bus cycle 0 0 0 interrupt acknowledge 0 0 1 read data from i/o 0 1 0 w r ite data to i/o 0 1 1 h a l t 1 0 0 instruction fetch 1 0 1 re a d d a t a fro m m e m o ry 1 1 0 w r i t e d a t a t o m e m o r y 1 1 1 none (passive) s6/clkdiv2_n (pio29) - bus cycle st atus bit 6 (synchronous output) /c lock divide by 2 (input w i th internal pull-up) s 6 - this signal is high during the sec ond and remaining cycle periods, i.e. t 2 ?t 4 , indicating that a dma initiated bus cycle is under way. s 6 is tristated during bus hold or reset. c l k d i v 2 _ n t h e m i c r o c o n t r o l l e r e n t e r s c l ock divide-by-2 m ode, if this signal is held low during power- on-reset. in this m ode, the pll is disabled and the processo r receives th e exte rnal clock divided by 2. sa m pling of this pin occurs on the rising edge of r e s _ n . should this pin be used as pio29 configured as an input, care should be taken that it is not driven low during power-on-reset. this pin has a n i n t e rn a l p u l l -u p s o i t i s n o t n e cessary to drive the pin high even though it defaults to an input pio. s c l k s e r i a l c l o c k ( s y n c h r o n o u s o u t p u t s w i t h t r i s t a t e ) t h i s p i n p r o v i d e s a s l a v e d e v i c e w i t h a s y n c h r o n o u s s e r i a l c l o c k p e r m i t t i n g s y n c h r o n i z a t i o n o f t h e t r a n s m i t a n d r e c e i v e d a t a e x c h a n g e s b e t w e e n t h e s l a v e a n d t h e m i c r o c o n t r o l l e r . s c l k i s t h e r e s u l t o f dividing the internal clock by 2, 4, 8, or 16 dependent on the contents of the synchronous serial control (ssc) register bits 5-4. accessing either the ssr of ssd regi s t e r s a c t i v a t e s t h e s c l k fo r e i g h t c y c l e s . w h e n s c l k is not active the m i croc ontroller hold is high. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 sdata ?serial data (syn chronous inout) this pin connects a slave device to synchronous serial transm it and receive data. the last value is m a i n t a i n e d o n t h i s p i n w h e n i t i s i n a c t i v e . sden1 - sden0 ? serial data enables ( s y n c h r o n o u s o u t p u t s w i t h t r i s t a t e ) t h e s e p i n s f a c i l i t a t e t h e t r ansfer of data on ports 1 and 0 of the sync hronous serial interf a c e ( s s i ) . e i t h e r sden1 o r sden0 is asserted by the m i crocontroller a t t h e s t a r t o f t h e d a t a t r a n sfer and is de-asserted it when t h e t ra n s fe r i s c o m p l e t e d . t h e s e p i n s a re h e l d l o w b y t h e m i c r o c o n t r o l l e r w h e n t h e y a r e i n a c t i v e . srdy/pio6 - synchronous ready (syn chronous level-sensitive input) this signal is an active high input synchronized to c l k o u t a and indicates to the m i cr ocontroller that a data t ra n s fe r w i l l b e c o m p l e t e d b y t h e a d d r e s s e d m e m o ry s p a c e o r i/ o d e v i c e . in contrast to the asynchronous ready ( ardy ), which requires internal synchronization, srdy perm its e a s i e r s y s t e m t i m i n g a s i t a l ready synchronized. tying srdy h i g h w i l l a l w a y s a s s e rt t h i s re a d y c o n d i t i o n , w h e r e a s t y i n g i t l o w w i l l g i v e c o n t r o l t o ardy . tmrin0/pio11 - timer input 0 (syn chronous edge-sensitive input) t h i s s i g n a l m a y b e e i t h e r a c l o c k o r c o n t r o l s i g n a l f o r t h e i n t e r n a l t i m e r 0 . t h e t i m e r i s i n c r e m e n t e d b y t h e m i c r o c o n t r o l l e r a f t e r i t s ynchronizes a rising edge of tmrin0 . w h e n n o t u s e d , t m r i n 0 m u s t b e t i e d high, or when used as p i o 1 1 i t i s p u l l e d u p i n t e r n a l l y . tm r i n 1 / p i o 0 - ti m e r i n p u t 1 (s y n c h r o n o u s e d g e -s e n s i ti v e i n p u t) t h i s s i g n a l m a y b e e i t h e r a c l o c k o r c o n t r o l s i g n a l f o r t h e i n t e r n a l t i m e r 1 . t h e t i m e r i s i n c r e m e n t e d b y t h e m i c r o c o n t r o l l e r a f t e r i t s ynchronizes a rising edge of tmrin1 . w h e n n o t u s e d , t m r i n 1 m u s t b e t i e d high, or when used as p i o 0 i t i s p u l l e d u p i n t e r n a l l y . t m r o u t 0 / p i o 1 0 - t i m e r o u t p u t 0 ( s y n c h r o n o u s o u t p u t ) this signal provides the system w ith a single pulse or a continuous w a v e fo rm w i t h a p ro g ra m m a b l e d u t y cycle. it is tristated during a bus hold or reset. tm r o u t1 / p i o 1 - ti m e r o u tp u t 1 (s y n c h r o n o u s o u tp u t) this signal provides the system w ith a single pulse or a continuous w a v e fo rm w i t h a p ro g ra m m a b l e d u t y cycle. it is tristated during a bus hold or reset. tx d / p i o 2 2 - tr a n s m i t d a ta (a s y n c h r o n o u s o u tp u t) this pin provides the system with asynchronous serial transm it data from the serial port. ucs_n/once1_n - upper memory c h ip select (synchronous output) / once mode request 1 (input w i th i n te r n a l p u l l -u p ) ucs_n - this pin provid e s an indication that a m e mory access is in train to the upper m e m ory block. the s i z e o f t h e u p p e r m e m o ry bl o c k a n d i t s b a s e a d d re s s are p r ogrammable, with th e s i z e a d j u s t a b l e u p t o 512 kbytes. ucs_n is held high during bus hold. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a f t e r p o w e r - o n - r e s e t , u c s _ n is active low and program execution begins at ffff0h with the default configuration of the ucs_n chip select is for 64 kbytes m e mory range fro m f0000h to fffffh. once1_n ?(onc e ? o n c i r c u i t e mulation). this pin and its com p anion pin once0_n define the m i c r o c o n t r o l l e r m o d e d u r i n g r e s e t . t h e s e t w o pins are sam pled on the rising edge of r e s _ n and if both are ass e rted low the m i crocontro ller s t arts in once m ode , else it starts norm ally. in once mode all pins a r e t r i s t a t e d a n d r e m a i n s o u n t i l a s u b s e q u e n t r e s e t . t o p re v e n t t h e m i c ro c o n t ro l l e r f r o m e n t e ri n g o n ce m o d e i n a d v e r t e n t l y , t h i s pin has a w eak pull-up that is only present during reset. f i nally, this pin is not tristated during bus hold. uz i_n/pio26 ?upper z e ro indicate (synchronous output) t h i s p i n a l l o w s t h e d e s i g n e r t o d e t e r m i n e i f a n a c c e s s to the interrupt vector tabl e is in progress by oring it with bits 15-10 of the address and data bus ( a d 1 5 - a d 1 0 on the ai186em and ao15-ao10 o n t h e ai188em). u z i _ n is the logical or of the inverted a19-a16 bits. it asserts in the first period of a bus c y c l e a n d i s h e l d t h roughout the cycle. a t r e s e t uz i_n should be pulled high or should be allowed to float. if this pin is pulled low at reset, the m i c r o c o n t r o l l e r e n t e r s a r e served clock test m ode . v cc ?po w er supply (input) these pins supply power (+5v ) t o t h e m i c ro c o n t ro l l e r. whb_n ? w r ite high b yte - i a 1 8 6 e m o n l y - (s y n c h r o n o u s o u tp u t w i th tr i s ta te ) this pin and w l b _ n provide an indication to the system of wh ich bytes of the data bus (upper, lower or both) are taking part i n a w r i t e c y c l e . w h b _ n i s a s s e r t e d w i t h ad15_ad8 and is the logical or of bhe_n and w r _ n . i t i s t r i s t a ted during reset. w l b_n/ wb_n ? write l ow byte - ia 186e m o n l y - (synchr onous output w i th tristate) / w r ite byte ? ia188em only - ( s y n c h r o n o u s o u t p u t w i t h t r i s t a t e ) w l b _ n - w l b _ n and w h b _ n provide an indication to the system of which bytes of the data bus (upper, l o w e r , o r b o t h ) a r e t a k i n g p a r t i n a w r i t e c y c l e . w l b _ n i s a s s e r t e d w i t h a d 7 _ a d 0 and is the logical or of a d 0 and w r _ n . i t i s t r i s t a t e d d u r i n g r e s e t . w b _ n ?on t he ia188em m i crocontroller, w b _ n p ro v i d e s a n i n d i c a t i o n t h a t a wr ite to the bus is o c c u rri n g . it s h a re s t h e s a m e e a rl y t i m i n g a s t h a t o f t h e n o n - m u l t i p l e x e d a d d r e s s b u s , a n d i s a s s o c i a t e d w i t h ad7-ad0 . it is tristated during reset. w r _n ?wri t e strobe (synchronous output) this pin provides an indication to t h e s y s t e m t h a t t h e d a t a c u r r e n t l y on the bus is to be written to a m e mory or i/o device. it is tr istated during a bus hold or reset. x1 ?crystal input (input) this pin and x2 are the connections for a fundamental m ode or third-overtone, para llel-resonant crystal used by the internal oscillator circui t. an external clock source for the m i crocontroller is connected to x1 w h i l e t h e x2 pin is left unconnected. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 x2 ?crystal input (input) this pin and x1 are the connections for a fundamental m ode or third-overtone, para llel-resonant crystal used by the internal oscillator circui t. an external clock source for the m i crocontroller is connected to x1 w h i l e t h e x2 pin is left unconnected. p i n s u s e d b y e m u l a t o r s t h e f o l l o w i n g p i n s a r e u s e d b y e m u l a t o r s : a19-a0 ao15-ao8 ad7-ad0 a l e bhe_n/aden_n (o n t h e a i1 8 6 e m ) c l k o u t a rfsh2_n/aden_n (o n t h e a i1 8 8 e m ) rd_n s2_n-s0_n s6/lock_n/clkdiv2_n u z i _ n e m u l a t o r s r e q u i r e t h a t s6/lock_n/clkdiv2_n a n d u z i _ n be configured as their norm a l functions, i.e. as s 6 and u z i _ n respectively. holding bhe_n/aden_n (ai186em) or rfsh_n/aden_n (ai188em) low during the rising edge of res_n, s6 and u z i _ n w i l l b e c o n f i g u r e d i n t h e i r n o r m a l f u n c t i o n s i n s t e a d o f a s p i o s , a t r e s e t . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction set summary n o t e key to abbreviations appears at the end of the table. instruction opcode - hex cloc k cycl es flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c aaa ascii adjust a l after add 37 - - 8 8 u - - - u u r u r aad ascii adjust ax before divide. d5 0a - 15 15 u - - - r r u r u a a m a s c i i a d ju st a l a fte r mu ltip ly d 4 0 a - 1 9 1 9 u - - - r r u r u aas ascii adjust a l after subtract 3f - - 7 7 u - - - u u r u r add imm 8 to a l with carry 14 ib - 3 3 add imm 16 t o a x with carry 15 iw - 4 4 add imm8 to r / m8 with carry 8 0 / 2 ib - 4 / 1 6 4 / 1 6 add imm 16 t o r / m1 6 with carry 8 1 / 2 i w - 4 / 1 6 4 / 2 0 a d d sig n e x te n d e d imm 8 to r / m 1 6 w i t h c a r r y 8 3 / 2 ib - 4 / 1 6 4 / 2 0 a d d b y te re g to r/ m8 w ith ca rry 1 0 / r - 3 / 1 0 3 / 1 0 a d d w o r d r e g t o r / m 1 6 w i t h c a r r y 1 1 / r - 3 / 1 0 3 / 1 4 a d d r / m 8 t o b y t e r e g w i t h c a r r y 1 2 / r - 3 / 1 0 3 / 1 0 a d c a d d r / m 1 6 t o w o r d r e g w i t h c a r r y 1 3 / r - 3 / 1 0 3 / 1 4 r - - - r r r r r a d d i m m 8 t o a l 0 4 i b - 3 3 a d d i m m 1 6 t o a x 0 5 i w - 4 4 a d d i m m 8 t o r / m 8 8 0 / 0 ib - 4 / 1 6 4 / 1 6 a d d i m m 1 6 t o r / m 1 6 8 1 / 0 i w - 4 / 1 6 4 / 2 0 a d d sig n e x te n d e d imm 8 to r / m 1 6 8 3 / 0 ib - 4 / 1 6 4 / 2 0 a d d b y t e r e g . t o r / m 8 0 0 / r - 3 / 1 0 3 / 1 0 a d d w o r d r e g . t o r / m 1 6 0 1 / r - 3 / 1 0 3 / 1 4 a d d r / m 8 t o b y t e r e g 0 2 / r - 3 / 1 0 3 / 1 0 a d d a d d r / m 1 6 t o w o r d r e g 0 3 / r - 3 / 1 0 3 / 1 4 r - - - r r r r r and imm 8 with al 24 ib 3 3 and imm 16 with ax 25 iw 4 4 and imm 8 with r/m8 80 / 4 ib 4 / 1 6 4 / 1 6 a n d imm 1 6 w ith r/ m1 6 8 1 / 4 i w 4 / 1 6 4 / 2 0 and sign -exten d e d imm 8 with r/m16 8 3 / 4 ib 4 / 1 6 4 / 2 0 a n d a n d b y t e r e g . w i t h r / m 8 2 0 / r 3 / 1 0 3 / 1 0 0 - - - r r u r 0 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a n d w o r d r e g . w i t h r / m 1 6 2 1 / r 3 / 1 0 3 / 1 4 a n d r / m 8 w i t h b y t e r e g 2 2 / r 3 / 1 0 3 / 1 0 a n d r / m 1 6 w i t h w o r d r e g 2 3 / r 3 / 1 0 3 / 1 4 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c b o u n d c h e c k a r r a y i n d e x a g a i n s t b o u n d s 6 2 / r - 3 3 - 3 5 3 3 - 3 5 - - - - - - - - - c all n e ar, d isp r e lative to n e xt in stru c tion e 8 c w - 1 5 1 9 call ne ar, reg i n direct mem ff /2 - 13 /1 9 1 7 / 2 7 call far to full address giv e n 9a cd - 23 31 c a l l - - call far to addr e ss at m1 6:1 6 wo rd ff /3 - 38 54 - - - - - - - cbw convert b y te inte ger to w o rd 98 - - 2 2 - - - - - - - - - c le a r ca rr y fla g f 8 - - 2 2 - - - - - - - - - c l c cld clear directio n flag fc - - 2 2 - 0 - - - - - - - cli clear interrupt- e nable fl ag fa - - 2 2 - - 0 - - - - - - c m c c o m p l e m e n t c a r r y f l a g f 5 - - 2 2 - - - - - - - - r c o m p a r e i m m 8 t o a l 3 c i b 3 3 c o m p a r e i m m 1 6 t o a x 3 d i w - 4 4 c o m p a r e i m m 8 t o r / m 8 8 0 / 7 i b 3 / 1 0 3 / 1 0 c o m p a r e i m m 1 6 t o r / m 1 6 8 1 / 7 i w 3 / 1 0 3 / 1 4 c o mp a re si g n -e x t e n d e d i mm8 to r/m16 8 3 / 7 i b 3 / 1 0 3 / 1 4 c o m p a r e b y t e r e g t o r / m 8 3 8 / r 3 / 1 0 3 / 1 0 c o m p a r e w o r d r e g t o r / m 1 6 3 9 / r - 3 / 1 0 3 / 1 4 c o m p a r e r / m 8 t o b y t e r e g 3 a / r - 3 / 1 0 3 / 1 0 c m p r - - - r r r r r c o m p a r e r / m 1 6 t o w o r d r e g 3 b / r - 3 / 1 0 3 / 1 4 compare byte e s : [di] to byte segment: [si] a 6 - - 2 2 2 2 c m p s c o m p a r e w o r d e s : [ d i ] t o w o r d segment: [si] a 7 - - 2 2 2 6 r - - - r r r r r c m p s b c o m p a r e b y t e e s : [ d i ] t o b y t e d s : [ s i ] a 6 - - 2 2 2 2 r - - - r r r r r cmp s w c o m p a r e w o r d e s : [ d i ] t o w o r d d s : [ s i ] a 7 - - 2 2 2 6 r - - - r r r r r cs cs se gm ent re g override pr efix 2e - - - - - - - - - - - - - cwd convert wor d int e ger to double w o rd 9 9 - - 4 4 - - - - - - - - - daa decim al ad just al after a ddition 27 - - 4 4 u - - - r r r r r das decim al ad just al after subtract ion 2f - - 4 4 u - - - r r r r r s u b t r a c t 1 f r o m r / m 8 f e / 1 - 3 / 1 5 3 / 1 5 s u b tra ct 1 fro m r/ m1 6 f f / 1 - 3 / 1 5 3 / 1 9 d e c s u b tra ct 1 fro m w o rd re g 4 8 + r w 3 3 r - - - r r r r r div divide u nsign ed numb e rs f6 m o d 1 1 0 r/m - 2 9 / 3 5 2 9 / 3 5 u - - - u u u u u ds ds s e gment override prefix 3e - - - - - - - - - - - - - 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c create stac k fra me for n e sted p r o c e d u r e c 8 i w ib - 2 2 + 1 6 ( n - 1 ) 2 6 + 2 0 ( n - 1 ) create stac k fra me for n o n- nest ed p r o c e d u r e c 8 i w 0 0 - 1 5 1 9 e n t e r create stac k fra me for n e sted p r o c e d u r e c 8 i w 0 1 - 2 5 2 9 - - - - - - - - - es es segment reg override pr efix 26 - - - - - - - - - - - - - e s c a p e - t a k e s a t r a p 7 d 8 / 0 - - - e s c a p e - t a k e s a t r a p 7 d 9 / 1 - - - e s ca p e - ta k e s a t ra p 7 d a / 2 - - - e s c a p e - t a k e s a t r a p 7 d b / 3 - - - e s ca p e - ta k e s a t ra p 7 d c / 4 - - - e s c a p e - t a k e s a t r a p 7 d d / 5 - - - e s c a p e - t a k e s a t r a p 7 d e / 6 - - - e s c e s ca p e - ta k e s a t ra p 7 d f / 7 - - - - - 0 0 - - - - - hlt susp end instruct ion ex ecution f4 - - 2 2 - - - - - - - - - divide i n t e g e rs a l = a x / ( r / m 8 ) ; a h = r e m a i n d e r f 6 / 7 - 4 4 - 5 2 / 5 0 - 5 8 4 4 - 5 2 / 5 0 - 5 8 i d i v divide i n t e g e rs ax = dx : ax /( r/m16); dx = rem a ind e r f 7 / 7 - 5 3 - 6 1 / 5 9 - 6 7 5 3 - 6 1 / 6 3 - 7 1 u - - - u u u u u multiply integers a x = ( r / m 8 ) * a l f 6 / 5 - 2 5 - 2 8 / 3 1 - 3 4 2 5 - 2 8 / 3 1 - 3 4 multiply integers dx= (r/ m1 6)*ax f 7 / 5 - 3 4 - 3 7 / 4 0 - 4 3 3 4 - 3 7 / 4 4 - 4 7 multiply integers (word reg) = (r /m16)*(sign-ext . byte integer) 6 b /r ib - 2 2 - 2 5 2 2 - 2 5 multiply integers (word reg ) = (w ord reg )*(sign- e xt. byte integer) 6 b /r ib - 2 2 - 2 5 2 2 - 2 5 multiply integers (word reg) = (r /m16)*(sign-ext . byte integer) 6 9 /r i w - 2 9 - 3 2 2 9 - 3 2 i m u l multiply integers (word reg ) = (w ord reg )*(sign- e xt. byte integer) 6 9 /r i w - 2 9 - 3 2 2 9 - 3 2 r - - - u u u u r 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c input b y te from i mm p o rt to al e4 ib - 10 10 input wor d from imm p o rt to ax e5 ib - 10 14 input b y te from port in dx to al ec - 8 8 in in p u t w o r d fro m p o rt in d x to a x e d - 8 1 2 - - - - - - - - - i n c r e m e n t r / m 8 b y 1 f e / 0 - 3 / 1 5 3 / 1 5 i n c r e m e n t r / m 1 6 b y 1 f f / 0 - 3 / 1 5 3 / 1 9 i n c increment word reg by 1 4 0 + r w - - 3 3 r - - - r r r r r in p u t b y te from p ort in d x to e s : [ d i ] 6 c i n s input wor d from port in dx to e s : [ d i ] 6 d insb in p u t b y te from p ort in d x to e s : [ d i ] 6 c i n s w input wor d from port in dx to e s : [ d i ] 6 d - - 1 4 1 4 - - - - - - - - - i n t 3 gener a te interru pt 3 (trap t o d e b u g ) c c - - 4 5 4 5 int gener a te type of interrupt specified b y imm 8 c d i b - 4 7 4 7 into g e n e r a te in te rru p t 4 if ove rflow flag (o) is 1 c e - - 4 8 , 4 4 8 , 4 - - 0 0 - - - - - iret interrupt return cf - - 28 28 restores v a lue o f flags reg that was stored on th e stack whe n t h e i n t e r r u p t w a s t a k e n j a jump short if ab ove (c & z = 0) j n b e j u m p s h o r t i f n o t b e l o w o r e q u a l 7 7 c b - 1 3 , 4 1 3 , 4 - - - - - - - - - jae jump short if ab ove or equ a l(c= 0) jnb jump short if not below (c= 0 ) jnc jump short if not carry (c=0) 7 3 c b - 1 3 , 4 1 3 , 4 - - - - - - - - - jb jump short if below (c=1) jc ju m p sh ort if c arry (c =1) jnae jump short if no t abov e or e q u a l (c=1) 7 2 c b - 1 3 , 4 1 3 , 4 - - - - - - - - - j b e j u m p s h o r t i f b e l o w o r e q u a l (c & z = 0) jna jump short if no t abov e (c & z = 0) 7 6 c b - 1 3 , 4 1 3 , 4 - - - - - - - - - jcxz jump short if cx reg is 0 e 3 cb - 15,5 15,5 - - - - - - - - - j e j u m p s h o r t i f e q u a l ( z = 1 ) jz jump short if 0 ( z =1) 7 4 c b - 1 3 , 4 1 3 , 4 - - - - - - - - - 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c jg jump short if gr eater (z & s = o) j n l e j u m p s h o r t i f n o t l e s s o r e q u a l ( z & s = o ) 7 f cb - 1 3 , 4 1 3 , 4 - - - - - - - - - j g e jump short if gr eater or equ a l (s=o) j n l j u m p s h o r t i f n o t l e s s ( s = o ) 7 d cb - 1 3 , 4 1 3 , 4 - - - - - - - - - j l e ju m p sh ort if le s s or e q u al ( z & s = o ) j n g j u m p s h o r t i f n o t g r e a t e r ( z & s = o ) 7 e c b - 1 3 , 4 1 3 , 4 - - - - - - - - - jump short direc t , disp relative t o n e x t i n s t r u c t i o n e b c b - 1 4 1 4 jump ne ar direct , disp relative to next instruction e 9 c w - 1 4 1 4 jump ne ar indire ct ff /4 - 11 /1 7 1 1 / 2 1 jump far direct t o doublew ord im m address e a c d - 1 4 1 4 j m p ju mp m1 6 : 1 6 in d ire ct a n d f a r f f / 5 - 2 6 3 4 - - - - - - - - - jne ju m p sh ort if n ot e q u al (z = 0 ) jnz ju m p sh ort if n ot ze ro (z = 0 ) 7 5 c b - 1 3 , 4 1 3 , 4 - - - - - - - - - jno jump short if no t overflow (o=1) 71 cb - 13, 4 13, 4 - - - - - - - - - j n p j u m p s h o r t i f n o t p a r i t y ( p = 0 ) jp o ju m p sh ort if p arity od d (p =0) 7 b c b - 1 3 , 4 1 3 , 4 - - - - - - - - - jn s ju mp sh o rt if n o t sig n (s = 0 ) 7 9 cb - 1 3 , 4 1 3 , 4 - - - - - - - - - jo jump short if ov erflow (o=1) 70 cb - 13, 4 13, 4 - - - - - - - - - jp ju m p sh ort if p arity (p =1) j p e j u m p s h o r t i f p a r i t y ( p = 1 ) 7 a c b - 1 3 , 4 1 3 , 4 - - - - - - - - - js ju mp sh o rt if sig n (s = 1 ) 7 8 cb - 1 3 , 4 1 3 , 4 - - - - - - - - - lahf loa d ah with low byte of fl ags r e g 9f - - 2 2 - - - - - - - - - l d s l o a d d s : r 1 6 w i t h s e g m e n t : o f f s e t from me mor y c 5 / r - 1 8 2 6 - - - - - - - - - l e a load offset for m16 w o rd in 16-bit r e g 8 d / r - 6 6 - - - - - - - - - l e a v e d e s t r o y p r o c e d u r e s t a c k f r a m e c 9 - - 8 8 - - - - - - - - - l e s l o a d e s : r 1 6 w i t h s e g m e n t o f f s e t from me mor y c 4 / r - 1 8 2 6 - - - - - - - - - l o c k a sse rts loc k_n d u rin g an instruction execution f 0 - - 1 1 - - - - - - - - - loa d b y te se gme nt :[si] in al ac 12 12 lods l o a d w o r d s e g m e n t : [ s i ] i n a x a d - - 1 2 1 6 - - - - - - - - - 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c l o d s b l o a d b y t e d s : [ s i ] i n a l a c 1 2 1 2 lodsw load word ds: [ s i] in ax ad 1 2 1 6 loop d e c r e m e n t c o u n t ; j u m p s h o r t i f cx $ 0 e2 - - l o o p e d e c r e m e n t c o u n t ; j u m p s h o r t i f cx $ 0 a n d z = 1 loopz d e c r e m e n t c o u n t ; j u m p s h o r t i f cx $ 0 a n d z = 1 e 1 c b - 1 6 , 6 1 6 , 6 - - - - - - - - - l o o p n e d e c r e m e n t c o u n t ; j u m p s h o r t i f cx $ 0 a n d z = 0 loopnz d e c r e m e n t c o u n t ; j u m p s h o r t i f cx $ 0 a n d z = 0 e 0 c b - 1 6 , 6 1 6 , 6 - - - - - - - - - c o p y r e g t o r / m 8 8 8 / r - 2 / 1 2 2 / 1 2 c o p y r e g t o r / m 1 6 8 9 / r - 2 / 1 2 2 / 1 6 c o p y r / m 8 t o r e g 8 a / r - 2 / 9 2 / 9 c o p y r / m 1 6 t o r e g 8 b / r - 2 / 9 2 / 1 3 cop y se gme n t re g to r/ m1 6 8c /sr - 2 / 1 1 2 / 1 5 c o p y r / m 1 6 t o s e g m e n t r e g 8 e / s r - 2 / 9 2 / 1 3 cop y b y te at se g ment offset to a l a0 - - 8 8 cop y word at se gme n t offset to ax a1 - - 8 12 cop y al to byte at seg ment offse t a2 - - 9 9 cop y ax to w o rd at seg ment offset a3 - - 9 13 cop y imm 8 to reg b 0 + r b - - 3 3 c o p y i m m 1 6 t o r e g b 8 + r w 3 4 c o p y i m m 8 t o r / m 8 c 6 / 0 - 1 2 1 2 m ov c o p y i m m 1 6 t o r / m 1 6 c 7 / 0 - 1 2 1 3 - - - - - - - - - cop y b y te segment [si] to es:[ di] a4 - - 14 14 mo v s cop y word s e gm ent [si] to e s :[di] a5 - - 14 18 movsb cop y b y te ds:[ si] to es:[ di] a4 - - 14 14 movsw cop y word ds:[ si] to es:[ di] a5 - - 14 18 - - - - - - - - - ax = (r/m 8) * al f6 /4 2 6 - 2 8 / 3 2 - 3 4 2 6 - 2 8 / 3 2 - 3 4 m u l dx :: ax = (r /m 16) * ax f7 /4 - 3 5 - 3 7 / 4 1 - 4 3 3 5 - 3 7 / 4 5 - 4 7 r - - - - - - - r perform 2' s com p leme nt ne gatio n of r/m 8 f 6 / 3 - 3 / 1 0 3 / 1 0 n e g perform 2' s com p leme nt ne gatio n o f r / m 1 6 f 7 / 3 - 3 / 1 0 3 / 1 4 r - - - r r r r r 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c n o p p e r f o r m n o o p e r a t i o n 9 0 - - 3 3 - - - - - - - - - c o m p l e m e n t e a c h b i t i n r / m 8 f 6 / 2 - 3 / 1 0 3 / 1 0 n o t c o m p l e m e n t e a c h b i t i n r / m 1 6 f 7 / 2 - - - - - - - - 3 / 1 0 3 / 1 4 - or imm8 with al 0c ib - 3 3 or imm1 6 with ax 0d iw 4 4 or imm8 with r/m8 80 / 1 ib - 4 / 1 6 4 / 1 6 o r imm1 6 w ith r/ m1 6 8 1 / 1 i w - 4 / 1 6 4 / 2 0 or imm8 with r/m16 83 / 1 ib - 4 / 1 6 4 / 2 0 o r b y t e r e g w i t h r / m 8 0 8 / r - 3 / 1 0 3 / 1 0 o r w o r d r e g w i t h r / m 1 6 0 9 / r - 3 / 1 0 3 / 1 4 o r r / m 8 w i t h b y t e r e g 0 a / r - 3 / 1 0 3 / 1 0 or o r r / m 1 6 w i t h w o r d r e g 0 b / r - 3 / 1 0 0 - - - r r u r 3 / 1 4 0 output al to im m port e6 ib - 9 9 output ax to im m port e7 ib - 9 13 output al to por t in dx ee - - 7 7 o u t output ax to p o r t in dx ef - - 7 11 - - - - - - - - - output byte ds:[ si] to port in dx 6e - - outs output word ds: [si] t o p o rt in dx 6f - - outsb output byte ds:[ si] to port in dx 6e - - outsw output word ds: [si] t o p o rt in dx 6f - - 1 4 1 4 - - - - - - - - - pop to p word of stack into mem o ry word 8 f / 0 - 2 0 2 4 pop to p word of stack into w o rd r e g 5 8 + r w - - 1 0 1 4 pop to p word of stack into d s 1f - - pop to p word of stack into e s 07 - - pop pop to p word of stack into s s 17 - - 8 1 2 - - - - - - - - - p o p a p o p d i, s i, b p , b x , d x , c x , & a x 6 1 - - 5 1 8 3 popf pop top word of stack into processor status flags re g 9 d - - 8 1 2 values in w o rd a t top of stac k are co pied into f l ags r e g bits p u s h m e m o r y w o r d o n t o s t a c k f f / 6 - 1 6 2 0 p u s h r e g w o r d o n t o s t a c k 5 0 + r w - - 1 0 1 4 push sign- e xtended imm8 onto stack 6 a - - 1 0 1 4 p u s h i m m 1 6 o n t o s t a c k 6 8 - - 1 0 1 4 p u s h c s o n t o s t a c k 0 e - - 9 1 3 p u s h s s o n t o s t a c k 1 6 - - 9 1 3 p u s h d s o n t o s t a c k 1 e - - 9 1 3 push p u s h e s o n t o s t a c k 0 6 - - 9 1 3 - - - - - - - - - 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c pusha p u s h a x , c x , d x , b x , o r i g i n a l s p , bp, si, and di 6 0 - - 3 6 6 8 - - - - - - - - - pus h f push proc essor status fla g s re g 9c - - 9 13 - - - - - - - - - rotate 9 bits of c and r/m8 left o n c e d 0 / 2 - 2 / 1 5 2 / 1 5 r otate 9 b its of c an d r/ m 8 le ft c l t i m e s d 2 / 2 - 5 + n / 1 7 + n 5 + n / 1 7 + n rotate 9 bits of c and r/m8 left imm8 times c 0 / 2 ib - 5 + n / 1 7 + n 5 + n / 1 7 + n r o ta te 1 7 b its o f c a n d r/ m 1 6 le ft o n c e d 1 / 2 - 2 / 1 5 2 / 1 5 r o ta te 1 7 b its o f c a n d r/ m 1 6 le ft cl times d 3 / 2 - 5 + n / 1 7 + n 5 + n / 1 7 + n r c l r o ta te 1 7 b its o f c a n d r/ m 1 6 le ft imm8 times c 1 / 2 ib - 5 + n / 1 7 + n 5 + n / 1 7 + n - - - - - - - - - rotate 9 bits of c an d r/m 8 righ t o n c e d 0 / 3 - 2 / 1 5 2 / 1 5 rotate 9 bits of c an d r/m 8 righ t cl times d 2 / 3 - 5 + n / 1 7 + n 5 + n / 1 7 + n rotate 9 bits of c an d r/m 8 righ t imm8 times c 0 / 3 ib - 5 + n / 1 7 + n 5 + n / 1 7 + n r o t a t e 1 7 b i t s o f c a n d r / m 1 6 right once d 1 / 3 - 2 / 1 5 2 / 1 5 r o t a t e 1 7 b i t s o f c a n d r / m 1 6 righ t c l tim e s d 3 / 3 - 5 + n / 1 7 + n 5 + n / 1 7 + n r c r r o t a t e 1 7 b i t s o f c a n d r / m 1 6 righ t im m 8 tim e s 7 5 / 3 ib - 5 + n / 1 7 + n 5 + n / 1 7 + n - - - - - - - - - input c x byt e s from p o rt in dx to e s : [ d i ] f 3 6 c - 8 + 8 n 8 + 8 n rep i n s input c x byt e s from p o rt in dx to e s : [ d i ] f 3 6 d - 8 + 8 n 1 2 + 8 n - - - - - - - - - load cx bytes fr om se gm ent :[si ] in al f 3 a c - 6 + 1 1 n 6 + 1 1 n rep lods load cx w o rds f r om segment :[si] in ax f 3 a d - 6 + 1 1 n 1 0 + 1 1 n - - - - - - - - - cop y cx bytes fr om se gm ents : [s i] t o e s :[ d i] f 3 a 4 - 8 + 8 n 8 + 8 n rep mo v s cop y cx w o rds f r om se gme n ts : [s i] t o e s :[ d i] f 3 a 5 - 8 + 8 n 1 2 + 8 n - - - - - - - - - o u t p u t c x b y t e s f r o m d s : [ s i ] t o port in dx f 3 6 e - 8 + 8 n 8 + 8 n rep outs o u t p u t c x b y t e s f r o m d s : [ s i ] t o port in dx f 3 6 f - 8 + 8 n 1 2 + 8 n - - - - - - - - - 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c f ill c x b yte s at e s :[d i] w ith a l f 3 a a - 8+8n 8+8n rep s t o s f i l l c x w o r d s a t e s : [ d i ] w i th al f3 ab - 8+8n 12+8n - - - - - - - - - find non-m a tching b y tes in e s :[di] and s e gm ent :[ si] f 3 a 6 - 5 + 2 2 n 5 + 2 2 n r e p e c m p s find non-m a tching words in e s : [ d i ] a n d s e g m e n t : [ s i ] f 3 a 7 - 5 + 2 2 n 9 + 2 2 n find non-al byt e starting at e s : [ d i ] f3 ae - 5+15 n 5 + 1 5 n r e p e s c a s find non-ax wor d starting at e s : [ d i ] f3 af - 5+15 n 9 + 1 5 n find non-m a tching b y tes in e s :di and s e gm ent :[ si] f 3 a 6 - 5 + 2 2 n 5 + 2 2 n r e p z c m p s find non-m a tching words in es: d i and s e gm ent :[ si] f 3 a 7 - 5 + 2 2 n 9 + 2 2 n find non-al byt e starting a t e s : d i f 3 a e - 5 + 1 5 n 5 + 1 5 n r e p z s c a s find non-ax wor d starting at e s :di f3 af - 5+15 n 9 + 1 5 n - - - - - - - - - find matchin g b y tes in es:[ di] and se gm e n t :[s i] f 2 a 6 - 5 + 2 2 n 5 + 2 2 n r e p n e c m p s f i n d m a t c h i n g w o r d s i n e s : [ d i ] and s e gm ent :[ si] f 2 a 7 - 5 + 2 2 n 9 + 2 2 n find al byte starting at es:[ di] f2 a6 - 5+22n 5 + 2 2 n r e p n z c m p s find ax word st arting at e s :[ di ] f2 a7 - 5+22 n 9 + 2 2 n find matchin g b y tes in es: d i an d se gm e n t :[s i] f2 ae - 5+15 n 5 + 1 5 n r e p n e s c a s find matchin g w o rds in es: d i an d se gm e n t :[s i] f2 af - 5+15 n 9 + 1 5 n find al byte starting at es:di f2 ae - 5+15n 5 + 1 5 n r e p n z s c a s find ax word st arting at e s : d i f2 af - 5+15 n 9 + 1 5 n - - - - - - - - - return near to c a lling pr ocedur e c3 16 20 return far to cal ling procedure cb d a t a low d a t a h ig h 2 2 3 0 r e t u r n n e a r ; p o p i m m 1 6 parameters c 2 1 8 2 2 r e t r e tu rn far; p op i m m 16 p aram e te rs c a d a t a low d a t a h ig h 2 5 3 3 - - - - - - - - - rotate 8 bits of r / m8 left once d 0 / 0 - 2 / 1 5 2 / 1 5 rotate 8 bits or r/m8 l e ft cl times d 2 / 0 - 5 + n / 1 7 + n 5 + n / 1 7 + n rotate 8 bits or r/m8 l e ft imm8 t i m e s c 0 / 0 i b data 8 5 + n / 1 7 + n 5 + n / 1 7 + n rol r o t a t e 1 6 b i t s o f r / m 8 l e f t o n c e d 1 / 0 - 2 / 1 5 2 / 1 5 u - - - - - - - r 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c rotate 16 bits or r/m8 l e ft cl t i m e s d 3 / 0 - 5 + n / 1 7 + n 5 + n / 1 7 + n rol rotate 16 bits or r/m8 l e ft imm8 t i m e s c 1 / 0 i b data 8 5 + n / 1 7 + n 5 + n / 1 7 + n u - - - - - - - r rotate 8 bits of r / m8 right onc e d 0 / 1 - 2 / 1 5 2 / 1 5 rotate 8 bits or r/m8 ri ght cl t i m e s d 2 / 1 - 5 + n / 1 7 + n 5 + n / 1 7 + n r otate 8 b its or r/ m 8 ri gh t im m 8 t i m e s c 0 / 1 i b data 8 5 + n / 1 7 + n 5 + n / 1 7 + n r o t a t e 1 6 b i t s o f r / m 8 r i g h t o n c e d 1 / 1 - 2 / 1 5 2 / 1 5 rotate 16 bits or r/m8 ri ght cl t i m e s d 3 / 1 - 5 + n / 1 7 + n 5 + n / 1 7 + n ror rotate 16 bits or r/m8 ri ght imm8 t i m e s c 1 / 1 i b data 8 5 + n / 1 7 + n 5 + n / 1 7 + n u - - - - - - - r s a h f show a h in l o w byte of the st atu s flags re g 9 e - - 3 3 - - - - r r r r r m u l t i p l y r / m 8 b y 2 , o n c e d 0 / 4 - 2 / 1 5 2 / 1 5 multiply r/m8 by 2, cl times d2 /4 - 5 + n / 1 7 + n 5 + n / 1 7 + n multiply r/m8 by 2, imm8 times c 0 / 4 ib data 8 5 + n / 1 7 + n 5 + n / 1 7 + n m u l t i p l y r / m 1 6 b y 2 , o n c e d 1 / 4 - 2 / 1 5 2 / 1 5 multiply r/m16 by 2, cl times d3 /4 - 5 + n / 1 7 + n 5 + n / 1 7 + n multiply r/m 1 6 by 2, i mm8 time s c 1 / 4 ib data 8 5 + n / 1 7 + n 5 + n / 1 7 + n m u l t i p l y r / m 8 b y 2 , o n c e d 0 / 4 - 2 / 1 5 2 / 1 5 multiply r/m8 by 2, cl times d2 /4 - 5 + n / 1 7 + n 5 + n / 1 7 + n multiply r/m8 by 2, imm8 times c 0 / 4 ib data 8 5 + n / 1 7 + n 5 + n / 1 7 + n m u l t i p l y r / m 1 6 b y 2 , o n c e d 1 / 4 - 2 / 1 5 2 / 1 5 multiply r/m16 by 2, cl times d3 /4 - 5 + n / 1 7 + n 5 + n / 1 7 + n s a l / s h l multiply r/m 1 6 by 2, i mm8 time s c 1 / 4 ib data 8 5 + n / 1 7 + n 5 + n / 1 7 + n u - - - - r r r r 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c perform a sign e d division of r/ m8 b y 2 , o n c e d 0 / 7 - 2 / 1 5 2 / 1 5 perform a sign e d division of r/ m8 by 2, cl times d 2 / 7 - 5 + n / 1 7 + n 5 + n / 1 7 + n perform a sign e d division of r/ m8 by 2, i mm8 time s c 0 / 7 ib data 8 5 + n / 1 7 + n 5 + n / 1 7 + n perform a sign e d division of r / m 1 6 b y 2 , o n c e d 1 / 7 - 2 / 1 5 2 / 1 5 perform a sign e d division of r/m1 6 b y 2, cl times d 3 / 7 - 5 + n / 1 7 + n 5 + n / 1 7 + n s a r perform a sign e d division of r/m16 b y 2, im m8 times c 1 / 7 i b data 8 5 + n / 1 7 + n 5 + n / 1 7 + n u - - - r r u r r subtract imm8 f r om al with borrow 1c ib - 3 3 s u b trac t im m 16 from a x w ith borrow 1 d iw data 8 4 4 subtract imm8 f r om r/m8 with borrow 8 0 / 3 ib - 4 / 1 6 4 / 1 6 subtract im m1 6 from r/m 16 with borrow 8 1 / 3 i w - 4 / 1 6 4 / 2 0 subtract sign-ex t ended i mm8 from r/m16 with borr ow 8 3 / 3 ib - 4 / 1 6 4 / 2 0 s u b trac t b yte re g from r / m 8 w ith borrow 1 8 / r data 8 3 / 1 0 3 / 1 0 subtract word reg from r / m16 w i t h b o r r o w 1 9 / r - 3 / 1 0 3 / 1 4 subtract r/m8 fr om r/m8 with borrow 1 a / r - 3 / 1 0 3 / 1 0 s b b subtract r/m8 r e g from byt e with borrow 1 b / r data 8 3 / 1 0 3 / 1 4 r - - - r r r r r c o m p a r e b y t e a l t o e s : [ d i ] ; update di a e - - 1 5 1 9 s c a s comp are w o rd a l to es:[ di]; update di a f - - 1 5 1 9 s c a s b c o m p a r e b y t e a l t o e s : [ d i ] ; update di a e - - 1 5 1 9 s c a s w comp are w o rd a l to es:[ di]; update di a f - - 1 5 1 9 r - - - r r r r r 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c divide u nsign ed of r/m 8 b y 2, o n c e d 0 / 7 - 2 / 1 5 2 / 1 5 divide u nsign ed of r/m 8 b y 2, c l t i m e s d 2 / 7 - 5 + n / 1 7 + n 5 + n / 1 7 + n divide u nsign ed of r/m 8 b y 2, imm8 times / 7 ib data 8 5 + n / 1 7 + n 5 + n / c 0 1 7 + n d i v i d e u n s i g n e d o f r / m 1 6 b y 2 , o n c e d 1 / 7 - 2 / 1 5 2 / 1 5 d i v i d e u n s i g n e d o f r / m 1 6 b y 2 , c l t i m e s d 3 / 7 - 5 + n / 1 7 + n u s h r - - - r r u r 0 5 + n / 1 7 + n / 7 i b data 8 5 + n / 1 7 + n 5 + n / d i v i d e u n s i g n e d o f r / m 1 6 b y 2 , imm8 times c 1 1 7 + n s s s s s e g m e n t r e g o v e r r i d e p r e f i x 3 6 - - - - - - - - - - - - - s t c s e t the carry fl ag to 1 - 2 2 - - f9 - - - - - - 1 s t d s e t t h e d i r e c t i o n f l a g s o t h e source i ndex (si ) and /or the d e s t i n a t i o n i n d e x ( d i ) r e g s w i l l decreme n t durin g string i n s t r u c t i o n s f d - - 2 2 - 1 - - - - - - - s t i e n a b l e m a s k a b l e i n t e r r u p t s a f t e r the next instruction f b - - 2 2 - - 1 - - - - - - store a l in b y te e s : [ d i ] ; u p d a t e d i a a - - 1 0 1 0 s t o s store ax in wor d es:[di]; updat e d i a b - - 1 0 1 4 s t o s b s t o r e a l i n b y t e e s : [ d i ] ; u p d a t e d i a a - - 1 0 1 0 stos w store ax in wor d es:[di]; updat e d i a b - - - - - - - - - - 1 0 1 4 - s u b tra ct im m8 f r o m a l 2 c ib - 3 3 subtract im m1 6 from ax 2d iw - 4 4 subtract im m8 f r om r/ m8 80 / 5 ib - 4 / 1 6 4 / 1 6 8 1 / 5 i w - 4 / 1 6 4 / 2 0 s u b t r a c t i m m 1 6 f r o m r / m 1 6 subtract sign-ex t ended i mm8 from r/m16 8 3 / 5 i b - 4 / 1 6 4 / 2 0 s u b r - - - subtract b y te re g from r / m8 28 /r - 3 / 1 0 3 / 1 0 subtract word re g from r / m1 6 29 /r - 3 / 1 0 3 / 1 4 subtract r/ m8 fr om b y te re g 2a /r - 3 / 1 0 3 / 1 0 subtract r/ m1 6 from word re g 2b /r - 3 / 1 0 3 / 1 4 r r r r r 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 instruction opcode - hex cl ock cycles flags af fecte d m n e m o n i c description byte 1 byte 2 b y t e 3 - 6 i a 1 8 6 i a 1 8 8 o d i t s z a p c a n d i m m 8 w i t h a l a 8 i b - 3 3 a n d i m m 1 6 w i t h a x a 9 i w - 4 4 and imm8 with r/m8 f6 / 0 ib data 8 4 / 1 0 4 / 1 0 a nd im m 16 w ith r/ m 16 f 7 / 0 i w - 4 / 1 0 4 / 1 4 and b y te re g with r/m8 84 /r - 3 / 1 0 3 / 1 0 test a n d w o r d r e g w i t h r / m 1 6 8 5 / r data 8 3 / 1 0 3 / 1 4 0 - - - r r u r 0 wait performs a nop 9b - - - - - - - - - - - - - e xchange w o rd r e g with ax - - 3 3 e xchange ax with word reg 9 0 + r w - - 3 3 e x c h a n g e b y t e r e g w i t h r / b y t e - - 4 / 1 7 4 / 1 7 e xchange r / m 8 with byte reg 8 6 /r - - 4 / 1 7 4 / 1 7 e x c h a n g e w o r d r e g w i t h r / m 1 6 - - 4 / 1 7 4 / 2 1 x c h g e xchange r / m 1 6 with word reg 8 7 /r - - 4 / 1 7 4 / 2 1 - - - - - - - - - xlat s e t a l t o m e m o r y b y t e s e g m e n t :[bx+unsi g ne d al] d 7 - - 1 1 1 5 xlatb set al t o me mory byte ds :[bx+unsi g ne d al] d 7 - - 1 1 1 5 - - - - - - - - - xor imm 8 with al 34 ib - 3 3 xor imm 16 with ax 35 iw - 4 4 xor imm 8 with r/m8 80 / 6 ib - 4 / 1 6 4 / 1 6 x o r imm 1 6 w ith r/ m1 6 8 1 / 6 i w - 4 / 1 6 4 / 2 0 xor sign- e xten d e d imm 8 with r/m16 8 3 / 6 i b - 4 / 1 6 4 / 2 0 x o r b y t e r e g w i t h r / m 8 3 0 / r - 3 / 1 0 3 / 1 0 xor word re g wi th r/m1 6 31 /r - 3 / 1 0 3 / 1 4 xor r/m 8 with byte re g 32 /r - 3 / 1 0 3 / 1 0 xor xor r/m 16 with word reg 33 /r - 3 / 1 0 3 / 1 4 0 - - - r r u r 0 key to abbreviations used i n s t r u c t i o n s u m m a r y t a b l e the operand address byte is configured as follows. 7 6 5 4 3 2 1 0 mod field aux field r/m field 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 mod fie l d (modifier field) m o d d e s c r i p ti o n 1 1 r/ m i s t re a t e d a s a re g i s t e r fi e l d 00 disp = 0, disp-low and disp-high are ab s e n t - a d d r e s s d i s p l a c e m e n t i s 0 . 01 disp = disp-low sign-extended to 16-bits, disp-high is absent. 10 disp = disp-high: disp-low. a u x f i e l d ( a u x i l i a r y f i e l d ) aux if mod = 11 and w ord = 0 if mod = 11 and w ord = 1 000 al ax 001 cl cx 010 dl dx 011 bl bx 100 ah sp 101 ch bp 110 dh si 111 bh di when m od $ 11, depends on instruction r/m field r/m description 000 ea = (bx) + (si) + dis p [whe r e e a i s t h e e ffective address] 001 ea = (bx) + (di) + disp 010 ea = (bp) + (si) + disp 011 ea = (bx) + (di) + disp 100 ea = (si) + disp 101 ea = (di) + disp 110 ea = (bp) + disp [exc ept if m od = 00, then ea = disp-high: disp-low] 111 ea = (bx) + disp displacement the displacem e nt is an 8 or 16 bit value a dded to the offset portion of the address. i m m e d i a t e the immedi ate bytes consist of up to 16 bits of immediate data. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 s e g m e n t o v e r r i d e p r e f i x the operand address byte is configured as follows. 7 6 5 4 3 2 1 0 0 0 1 s r s r 1 1 0 s r s e g m e n t r e g i s te r 00 es 0 1 c s 1 0 s s 1 1 d s n o t a t io n p a r a m e t e r i n d i c a t i o n : t h e c o m p o n e n t o f t h e l e f t i s t h e segm ent for a component located in m e mory. the com pone nt on the right is the offset. : : t h e c o m p o n e n t o f t h e l e f t i s c o n c a t e n ated with the com p o n e n t o n t h e r i g h t . operand translation i m m 8 im m e d i a t e b y t e : s i g n e d num ber between ?28 and 127 i m m 1 6 im m e d i a t e w o rd : s i g n e d n u m b e r b e t w e e n 3 2 7 6 8 a n d 3 2 7 6 7 m o p e ra n d i n m e m o ry m 8 by t e s t ri n g i n m e m o ry pointed to by ds:si or es:di m 1 6 w o r d s t r i n g i n m e m o r y p o i n t e d t o b y d s : s i o r e s : d i r/m 8 general byte register or a byte in m e mory r / m 1 6 g e n e r a l w o r d r e g i s t e r o r a w o r d i n m e m o r y opcode p a r a m e t e r / 0 - / 7 t h e a u x i l i a ry f i e l d i n t h e o p e ra n d a ddress byte specifies an extens ion (from 000 to 111, i.e. 0 to 7) to the opcode instead of a re gister. thus the opcode for adding (and) an i m m e d i a t e b y t e t o a g e n e r a l b y t e r e gister or a byte in m e m ory is 80 /4 ib? t h i s i n d i c a t e s t h a t t h e s e c o n d b y t e of the opcode is mod 100 r/m? / r t h e a u x i l i a r y f i e l d i n t h e o p e r a n d a d d r e s s b y t e s p e c i f i e s a r e g i s t e r r a t h e r t h a t a n o p c o d e extension. the opcode byte spec ifies which register, either byte size or w ord size, is assigned as in the aux code above. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 / s r t h i s b y t e i s p l a c e d b e f o r e t h e i n s t r u c t i o n as show n above under segm ent override prefix. cb the byte following the opc ode byte specifies the offset. cd the double-word following the opcode byte sp ecifies the offset a nd is som e cases a s e g m e n t . ib imm e diate byte ? signed or unsi g n e d d e t e r m i n e d b y t h e o p c o d e b y t e . iw imm e diate word ?signed or unsigned determ ined by the opcode byte. rw word register operand as determ ined by the opcode byte, aux field. f l a g s a f f e c t e d a f t e r i n s t r u c t i o n u undefined - u n c h a n g e d r result dependent 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a b s o l u t e m a x i m u m r a t i n g s s t o ra g e t e m p e ra t u re - 6 5 % c t o + 1 2 5 % c voltage on any pin with respect to ground -0.5 v to v c c +0.5 v o p e r a t i n g r a n g e i n d u s t r i a l ( t a ) - 4 0 % c t o + 8 5 % c t a = a m b i e n t t e m p e r a t u r e d c c h a r a c t e r i s t i c s o v e r c o m m e r c i a l o p e r a t i n g r a n g e s prel imina r y s y m b o l parame te r desc ription test cond itions m in m a x u n i t v il input l o w voltage (except x1) -0.5 0.8 v v i l 1 clock i nput l o w voltage (x1) -0.5 0.8 v v i h input high v o ltage (except r e s_n an d x1) 2.0 v c c + 0.5 v v i h 1 input high v o ltage (res_ n ) 2.4 v c c + 0.5 v v i h 1 clock i nput high voltage (x1) v c c - 0 . 8 v c c + 0.5 v v o l output low vol t ages ( 1 ) i o l = 2.5 ma (s2 _ n -s0_n) 0.45 v i o l = 2.0 ma (ot h er) 0.45 v v o h o u t p u t h i g h v o l t a g e s i o h = - 2 .4 ma @ 2.4 v 2.4 v c c + 0 . 5 v i o h = - 2 0 0 & a @ v c c 0.5 v c c - 0.5 v c c v i c c p o w e r s u p p l y c u r r e n t @ 0 % c v c c = 5.5 v ( 2 ) 5 . 9 m a / m h z i l i in p u t l e a k a g e c u rre n t @ 0 . 5 m h z 0 . 4 5 v ' v in ' v c c ( 1 0 & a i l o o u t p u t l e a k a g e c u r r e n t @ 0 . 5 m h z 0 . 4 5 v ' v o u t ' v c c ( 3 ) ( 1 0 & a v c l o clock outp ut lo w i c l o = 4.0 ma 0.45 v v c h o clock outp ut hi g h i c h o = - 5 0 0 & a v c c - 0.5 v n o t e s 1. the lcs_n/once0_n , mcs3_n ?mcs0_n , ucs_n/once1_n , and rd_n pins have weak internal pull-up resistors. loading the lcs_n/once0_n and ucs_n/once1_n pins in excess of i oh = - 2 0 0 & a d u ri n g r e s e t c a n c a u s e t h e d e v i c e t o g o i n t o o n c e m o d e . 2. current is measured with th e d e v i c e i n re s e t w i t h t h e x1 and x 2 driven and all other non-power pins open but held high or low. 3. t e s t i n g i s p e rfo rm e d w i t h t h e pins floating, either during h o l d or by invoking the once m ode. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a c c h a r a c t e r i s t i c s o v e r c o m m e r c i a l o p e r a t i n g r a n g e s ( 4 0 m h z ) no. nam e des c ription min max units gener a l timing requir e ments 1 tdvcl data in setup 10 ns 2 tcldx data in hold 0 ns gener a l timing res pons es 3 tchsv status active delay 0 6 ns 4 tclsh status inactiv e delay 0 6 ns 5 t c l a v a d addre s s valid del ay 0 12 ns 6 t c l a x a d d r e s s h o l d 0 1 2 n s 8 tchdx status hold t i me 0 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width t c l c h - 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s 12 tavll a d a d d r e s s v a l i d t o a l e l o w t c l c h n s 1 3 t l l a x a d addre s s hold from a l e i n a c t i v e t c h c l n s 14 tavch a d a d d re s s v a lid to c lo c k h ig h 0 n s 15 tclaz a d addre s s f l oat delay 0 12 ns 16 tclcsv mcs_n/pcs _ n inactive del a y 0 12 ns 1 7 tc xc sx mcs_n/pcs _ n hold fro m comm and in active t c l c h n s 1 8 t c h c s x mcs_n/pcs _ n inactive del a y 0 12 ns 19 tdxdl den_n i n a c t i v e t o d t _ r _ n l o w 0 n s 20 tcvctv control active delay 1 0 10 ns 2 1 tc vd ex den_n i n a c t i v e d e l a y 0 0 n s 22 tchctv control active delay 2 0 10 ns 2 3 tl h av a l e high to addre s s valid 7.5 ns 80 tclclx lcs_n i n a c t i v e d e l a y 0 9 n s 81 tclcsl lcs_n active delay 0 9 ns 8 2 t c l r f c l k o u t a h i g h t o r f s h _ n invalid 0 12 ns 8 4 tl r l l lcs_n pre c ha rge pul s e wi dth tc l c l + tclch n s read c y cle timing resp onses 24 tazrl a d addre s s f l oat to rd_n active 0 ns 25 tclrl rd_n active delay 0 10 ns 26 trlrh rd_n pulse width tclcl ns 27 tclrh rd_n ina c tive delay 0 10 ns 2 8 t r h l h rd_n i n a c t i v e t o a l e h i g h t c l c h n s 29 trhav rd_n i n a c t i v e t o a d addre s s active tclcl ns 30 tcldox data hold ti me 0 ns write c y cle timing resp onses 31 tcvctx control inacti ve delay 0 10 ns 32 twlwh w r _ n p u l s e wid th 2 tc l c l n s 3 3 t w h l h w r _ n i n a c t i v e t o a l e h ig h tc l c h n s 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 no. nam e des c ription min max units 34 twhdx data hold after w r _ n tclcl ns 3 5 t w h d e x w r _ n i n a c t i v e t o den_n i n a c t i v e t c l c h n s 41 tdshl h d s _ n i n a c t i v e t o a l e inactive tclch ns 59 trhdx rd_n h i g h t o d a t a h o l d o n a d b u s 0 n s 65 tavwl a addre s s valid to wr_n l o w tclcl + tchcl n s 66 tavrl a a d d r e s s v a l i d t o rd_n l o w tc l c l + tchcl n s 6 7 t c h c s v c l k o u t a h i g h t o lcs_n/usc _n valid 0 9 ns 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 8 7 t a v b l a a d d r e s s v a l i d t o w h b _ n / w l b _ n lo w tchcl - 1.5 tc h c l n s r e fre s h t imi n g c y c le pa r a me te r s 79 tchrfd c l k o u t a h i g h t o r f s h _ n va lid 0 12 ns 8 2 t c l r f c l k o u t a h i g h t o r f s h _ n invalid 0 12 ns 85 trfcy r f s h _ n c y c l e t i m e 6 t c l c l n s 8 6 t l c r f lcs_n i n a c t i v e t o r f s h _ n a c t i v e d e l a y 2 t c l c l n s c l k i n t i m i n g 36 tckin x 1 p e rio d 2 5 6 6 n s 37 tclck x 1 low time 7.5 ns 38 tchck x 1 high time 7.5 ns 39 tckhl x 1 fall time 5 ns 4 0 t c k l h x 1 r i s e t i m e 5 n s c l k o u t t i m i n g 42 tclcl c l k o u t a p e r i o d 2 5 n s 43 tclch c l k o u t a l o w t ime t c l c l /2 n s 44 tchcl c l k o u t a hig h time tcl c l/2 ns 4 5 t c h 1 c h 2 c l k o u t a r i s e t i m e 3 n s 4 6 t c l 2 c l 1 c l k o u t a fall time 3 ns 61 tlock maximum pl l lock time 0.5 ms 69 tcicoa x 1 t o c l k o u t a s k e w 2 5 n s 70 tcicob x 1 t o c l k o u t b s k e w 3 5 n s ready & peripheral timing requir e ments 47 tsrycl srd y transition setup tim e 10 ns 48 tclsry srd y t r a n s i s t i o n h o l d t i m e 3 n s 4 9 ta r y c h ard y resoluti on tra n sitio n setup time 9 ns 50 tclarx ard y ac tiv e h o ld t ime 4 n s 51 tarychl ard y inactive holdi ng time 6 ns 52 tarylcl ard y setup time 9 ns 53 tinvch periph eral se tup time 10 ns 54 tinvcl drq setup ti me 10 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 no. nam e des c ription min max units peripheral timing respo nses 55 tcltmv timer o u tput delay 0 12 ns res e t & hol d timing requirements 57 tresin r e s _ n setup time 10 ns 58 thvcl h l d setup time 10 ns res et & hol d timing respons es 62 tclhav h l d a valid de lay 0 7 ns 63 tchcz comm and li nes flo at del ay 0 12 ns 64 tchcv comm and li nes valid del ay (after floa t) 0 12 ns sy nchronou s serial port timing requ irements 75 tdvsh data valid to sclk h i g h 1 0 n s 77 tshdx sclk h i g h t o s p i d a t a h o l d 3 n s sy nchronou s serial port timing resp onses 71 tclev clkouta lo w to sde n valid 0 12 ns 7 2 t c l s l c l k o u t a l o w t o s c l k h i g h 0 1 2 n s 78 tsldv scl k lo w to data valid 0 12 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 w a v e f o r m s a l p h a b e t i c k e y t o w a v e f o r m p a r a m e t e r s no. nam e des cription no. n am e des cription 4 9 t a r y c h a r d y r e s o l u t i o n t r a n s i t i o n s e t u p time 2 tcld x d a ta in hold 5 1 t a r y c h l a r d y i n a ctive h o ld in g t ime 7 1 t c l e v clkouta low to sden valid 5 2 t a r y l c l a r d y s e t u p t i m e 6 2 tclh av h l d a v a l i d d e l a y 8 7 t a v b l a a d d r e s s v a l i d t o whb_n/ wlb _ n l o w 8 2 tclrf clkouta h i g h t o r f s h _ n in valid 1 4 t a v c h a d a d d r e s s v a l i d t o c l o c k h i g h 2 7 tclrh r d _ n in active d e lay 1 2 t a v l l a d address vali d to a l e l o w 2 5 tclrl r d _ n a c t i v e d e l a y 6 6 t a v r l a a d d r e s s v a l i d t o r d _ n l o w 4 tcls h status i n active dela y 6 5 ta v w l a a d d r e s s v a l i d t o w r _ n l o w 7 2 t c l s l clkouta low to sclk low 2 4 t a z r l a d a d d r e s s f l o a t t o r d _ n a c t i v e 4 8 t c l s r y srdy t r a n s i s t i o n h o l d t i m e 4 5 t c h 1 c h 2 clkouta rise ti me 55 tcltmv timer output de lay 6 8 t c h a v clkouta h i g h t o a a d d r e s s v a l i d 8 3 t c o a o b clkouta t o c l k o u t b s k e w 3 8 t c h c k x 1 h i g h t i m e 2 0 tc v c t v control active d e lay 1 4 4 t c h c l clkouta h i g h t i m e 3 1 tc v c t x control inactive delay 6 7 t c h c s v clkouta h i g h t o lcs_n/usc _ n valid 21 t c v d e x d e n _ n in active dela y 1 8 t c h c s x mcs_n/pcs_n i n active d e la y 17 tcxcs x mcs_n/pcs_n hold fr om c o m mand in active 22 tchctv control active d e lay 2 1 tdvcl data in s e tup 64 tchcv comm an d lin e s valid d e lay (afte r float) 7 5 t d v s h d a t a v a l i d t o s c l k h i g h 6 3 t c h c z c o m m a n d l i n e s f l o a t d e l a y 1 9 t d x d l d e n _ n in ac tive to d t _ r _ n low 8 t c h d x s t a t u s h o l d t i m e 5 8 th v c l h l d s e t u p t i m e 9 t c h l h a l e a c t i v e d e l a y 5 3 t i n v c h p e r i p h e r a l s e t u p t i m e 1 1 t c h l l a l e i n a ctive d e la y 5 4 tinvcl d r q setup ti me 7 9 t c h r f d clkouta h i g h t o r f s h _ n v a lid 86 tlcrf lcs_n i n a c t i v e t o r f s h _ n a c t i v e d e l a y 3 t c h s v s t a t u s a c t i v e d e l a y 2 3 t l h a v a l e high to addr ess valid 6 9 t c i c o a x 1 to c l k o u t a s k e w 1 0 t l h l l a l e w i d t h 7 0 t c i c o b x 1 to c l k o u t b s k e w 1 3 tllax a d a d d r e s s h o l d f r o m a l e i n a c t i v e 3 9 t c k h l x 1 fall time 61 tlock maximu m p ll l o ck tim e 3 6 t c k i n x 1 p e r i o d 8 4 tlrll lcs_n pr echarge pulse width 4 0 t c k l h x 1 rise tim e 57 t r e s i n res_ n setup ti me 4 6 t c l 2 c l 1 clkouta f a ll time 85 trfcy r f s h _ n cycle ti me 5 0 t c l a r x a r d y active hold time 29 t r h a v r d _ n in ac tive to a d address active 5 tclav a d a d d r e s s v a l i d d e l a y 5 9 trh d x r d _ n h i g h t o d a t a h o l d o n a d b u s 6 tc l a x a d d re ss h o ld 2 8 t r h l h r d _ n in ac tive to a l e h i g h 15 tclaz a d address floa t dela y 26 trlrh r d _ n pulse widt h 4 3 t c l c h clkouta low ti me 77 t s h d x sclk h i g h t o s p i d a t a h o l d 3 7 t c l c k x 1 low ti me 78 t s l d v sclk l o w s p i d a t a h o l d 4 2 t c l c l clkouta p e r i o d 4 7 tsrycl srdy transition setup time 8 0 t c l c l x lcs_n i n a c t i v e d e l a y 3 5 t w h d e x w r _ n i n a c t i v e t o de n_ n in active 8 1 t c l c s l lcs_n a c t i v e d e l a y 3 4 t w h d x d a t a h o l d a f t e r w r _ n 1 6 t c l c s v mcs_n/pcs_n i n active d e la y 33 t w h l h w r _ n i n a c t i v e t o a l e h i g h 3 0 tc l d o x d a ta h o ld t im e 3 2 twlwh w r _ n puls e widt h 7 tcldv data valid delay 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 n u m e r i c k e y t o w a v e f o r m p a r a m e t e r s no. nam e des cription no. n am e des cription 1 td vcl d a ta in setup 43 tclch clkouta low ti me 2 tcld x d a ta in hold 44 tch c l clkouta high ti me 3 t c h s v s t a t u s a c t i v e d e l a y 4 5 t c h 1 c h 2 clkouta r ise t i m e 4 t c l s h s t a t u s i n a c t i v e d e l a y 4 6 tc l 2c l 1 clkouta f a l l t i m e 5 tclav a d a d d r e s s v a l i d d e l a y 4 7 tsrycl srdy transition setup time 6 tc l a x a d d re ss h o ld 4 8 t c l s r y srdy t r a n s i s t i o n h o l d t i m e 7 tcldv data valid delay 49 t a r y c h a r d y r e s o l u t i o n t r a n s i t i o n s e t u p t i m e 8 t c h d x s t a t u s h o l d t i m e 5 0 tclarx a r d y a c t i v e h o l d t i m e 9 t c h l h a l e a c t i v e d e l a y 5 1 t a r y c h l a r d y inactive holding time 1 0 t l h l l a l e width 52 t a r y l c l a r d y s e t u p t im e 1 1 t c h l l a l e i n a ctive d e la y 5 3 tinv c h p e rip h e ral s e tu p t im e 1 2 t a v l l a d address vali d to ale l o w 54 tinvcl d r q setup ti me 1 3 t l l a x a d address h o ld from ale i n active 55 tcltmv timer output de lay 1 4 t a v c h a d a d d r e s s v a l i d t o c l o c k h i g h 5 7 t r e s i n res_ n setup ti me 15 tclaz a d address floa t dela y 58 th v c l h l d s e t u p t i m e 1 6 t c l c s v mcs_n/pcs_n i n active d e la y 59 trh d x r d _ n h i g h t o d a t a h o l d o n a d b u s 1 7 t c x c s x mcs_n/pcs_n hold fr om c o m mand in active 6 1 tlock maximu m p ll l o ck tim e 1 8 t c h c s x mcs_n/pcs_n i n active d e la y 62 tclh av h l d a v a l i d d e l a y 1 9 t d x d l d e n _ n in ac tive to d t _ r _ n l o w 6 3 tchcz comm an d lin e s float d e la y 20 tcvctv control active d e lay 1 64 tc h c v c om m an d l in e s v alid d e lay (afte r f loat) 2 1 t c v d e x d e n _ n i n a c t i v e d e l a y 6 5 tavwl a a d d r e s s v a l i d t o w r _ n l o w 2 2 tc h c t v c o n tro l a ctive d e la y 2 6 6 tavrl a a d d r e s s v a l i d t o r d _ n l o w 2 3 t l h a v a l e high to addr ess valid 67 t c h c s v clkouta h i g h t o lcs_n/usc _ n v a l i d 2 4 t a z r l a d a d d r e s s f l o a t t o r d _ n a c t i v e 6 8 t c h a v clkouta h i g h t o a a d d r e s s v a l i d 2 5 t c l r l r d _ n active delay 69 tcicoa x 1 to c l k o u t a s k e w 2 6 t r l r h r d _ n pulse widt h 70 tcicob x 1 to c l k o u t b s k e w 2 7 t c l r h r d _ n i n a c t i v e d e l a y 7 1 t c l e v clkouta low to sden valid 2 8 t r h l h r d _ n in ac tive to a l e h i g h 7 2 t c l s l clkouta low to sclk h i g h 2 9 t r h a v r d _ n in ac tive to a d address active 75 t d v s h d a t a v a l i d t o s c l k h i g h 3 0 tc l d o x d a ta h o ld t im e 7 7 t s h d x sclk h i g h t o s p i d a t a h o l d 31 tcvctx control i nactive dela y 78 t s l d v sclk l o w t o d a t a v a l i d 3 2 t w l w h w r _ n puls e widt h 79 t c h r f d clkouta h i g h t o r f s h _ n v a lid 3 3 t w h l h w r _ n i n a c t i v e t o a l e h i g h 8 0 tclclx lcs_n i n active d e lay 34 twh d x d a ta hold after w r _ n 8 1 tclcsl lcs_n active del ay 3 5 t w h d e x w r _ n i n a c t i v e t o de n_ n in active 82 tclrf clkouta h i g h t o r f s h _ n in valid 3 6 t c k i n x 1 p e r i o d 8 3 t c o a o b clkouta t o c l k o u t b s k e w 3 7 t c l c k x 1 low ti me 84 tlrll lcs_n pr echarge pulse width 3 8 t c h c k x 1 h i g h t i m e 8 5 trfcy r f s h _ n cycle ti me 3 9 t c k h l x 1 f a l l t i m e 8 6 tlcrf lcs_n i n a c t i v e t o r f s h _ n a c t i v e d e l a y 4 0 t c k l h x 1 rise tim e 87 ta v b l a a d d r e s s v a l i d t o whb_n/ wlb _ n low 4 2 t c l c l clkouta p e r i o d 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 read cy cle 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clkouta a19-0 s6_lock_n ad15-ad0/ad7-ad0 ao15-ao8 ale rd_n bhe_n lcs_n/ucs_n mcs_n/pcs_n den_n dt_r_n s2_n-s0_n uzi_n address address s6 lock_n s6 s6 address data address address bhe_n bhe_n 68 8 14 6 1 2 9 23 11 15 29 59 10 24 66 26 28 5 12 25 27 67 16 13 18 17 20 21 19 41 22 3 22 4 99 t1 t2 t3 t4 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 r e a d c y c l e t i m i n g no. nam e des c ription min max units gener a l timing requir e ments 1 tdvcl data in setup 10 ns 2 tcldx data in hold 0 ns gener a l timing res pons es 3 tchsv status active delay 0 6 ns 4 tclsh status inactiv e delay 0 6 ns 5 t c l a v a d addre s s valid del ay 0 12 ns 6 t c l a x a d d r e s s h o l d 0 1 2 n s 8 tchdx status hold t i me 0 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width tclch- 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s 12 tavll a d a d d r e s s v a l i d t o a l e l o w t c l c h n s 1 3 t l l a x a d addre s s hold from a l e inactive tchcl ns 14 tavch a d a d d re s s v a lid to c lo c k h ig h 0 n s 15 tclaz a d addre s s f l oat delay 0 12 ns 16 tclcsv mcs_n/pcs _ n inactive del a y 0 12 ns 1 7 tc xc sx mcs_n/pcs _ n hold fro m comm and in active tclch ns 1 8 t c h c s x mcs_n/pcs _ n inactive del a y 0 12 ns 19 tdxdl den_n i n a c t i v e t o d t _ r _ n l o w 0 n s 20 tcvctv control active delay 1 0 10 ns 2 1 tc vd ex den_n i n a c t i v e d e l a y 0 9 n s 22 tchctv control active delay 2 0 10 ns 2 3 tl h av a l e high to addre s s valid 7.5 ns read c y cle timing resp onses 24 tazrl a d addre s s f l oat to rd_n active 0 ns 25 tclrl rd_n active delay 0 10 ns 26 trlrh rd_n pulse width tclcl ns 27 tclrh rd_n ina c tive delay 0 10 ns 2 8 t r h l h rd_n i n a c t i v e t o a l e h i g h t c l c h n s 29 trhav rd_n i n a c t i v e t o a d addre s s active tclcl ns 66 tavrl a a d d r e s s v a l i d t o rd_n l o w tclcl + tc h c l n s 6 7 t c h c s v c l k o u t a h i g h t o lcs_n/usc _n valid 0 9 ns 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 write cycle 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clkouta a19-0 s6_lock_n ad15-ad0/ad7-ad0 ao15-ao8 ale wr_n whb_n/wlb_n/wb_n bhe_n lcs_n/ucs_n mcs_n/pcs_n den_n dt_r_n s2-s0 uzi_n address address s6 lock_n s6 s6 address data data bhe_n bhe_n 3 65 68 8 14 6 30 7 9 23 11 13 31 34 10 32 33 20 20 12 87 5 67 16 17 18 31 21 19 22 4 35 31 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 w r i t e c y c l e t i m i n g no. nam e des c ription min max units gener a l timing requir e ments 1 tdvcl data in setup 10 ns 2 tcldx data in hold 0 ns gener a l timing res pons es 3 tchsv status active delay 0 6 ns 4 tclsh status inactiv e delay 0 6 ns 5 t c l a v a d addre s s valid del ay 0 12 ns 6 t c l a x a d d r e s s h o l d 0 1 2 n s 7 tcldv data valid delay 0 12 ns 8 tchdx status hold t i me 0 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width tclch- 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s 12 tavll a d a d d r e s s v a l i d t o a l e l o w t c l c h n s 1 3 t l l a x a d addre s s hold from a l e inactive tchcl ns 14 tavch a d a d d re s s v a lid to c lo c k h ig h 0 n s 16 tclcsv mcs_n/pcs _ n inactive del a y 0 12 ns 1 7 tc xc sx mcs_n/pcs _ n hold fro m comm and in active tclch ns 1 8 t c h c s x mcs_n/pcs _ n inactive del a y 0 12 ns 19 tdxdl den_n i n a c t i v e t o d t _ r _ n l o w 0 n s 20 tcvctv control active delay 1 0 10 ns 22 tchctv control active delay 2 0 9 ns 2 3 tl h av a l e high to addre s s valid 7.5 ns write c y cle timing resp onses 30 tcldox data hold ti me 0 ns 31 tcvctx control inacti ve delay 0 10 ns 32 twlwh w r _ n p u l s e wid th 2 tc l c l n s 3 3 t w h l h w r _ n i n a c t i v e t o a l e h ig h tc l c h n s 34 twhdx data hold after w r _ n tclcl ns 3 5 t w h d e x w r _ n i n a c t i v e t o den_n i n a c t i v e t c l c h n s 65 tavwl a a d d r e s s v a l i d t o w r _ n l o w tclcl + tc h c l n s 6 7 t c h c s v c l k o u t a h i g h t o lcs_n/usc _n valid 0 9 ns 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 8 7 t a v b l a addre s s valid to w h b _ n / w l b _ n l o w tchcl -1.5 n s 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p s r a m r e a d c y c l e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clkouta a19-a0 s6/lock_n ad15-ad0/ad7-ad0 ao15-ao8 ale rd_n lcs_n address address s6 lock_n s6 s6 address data address address address 66 68 8 7 1 2 9 23 11 10 59 24 26 28 25 27 5 81 80 84 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p s r a m r e a d c y c l e t i m i n g no. nam e com m ent min max units gener a l timing requir e ments 1 tdvcl data in setup 10 nll ns 2 tcldx data in hold 0 ns gener a l timing res pons es 5 t c l a v a d addre s s valid del ay 0 12 ns 7 tcldv data valid delay 0 12 ns 8 tchdx status hold t i me 0 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width t c h c l - 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s 2 3 tl h av a l e high to addre s s valid 7.5 ns 80 tclclx lcs_n i n a c t i v e d e l a y 0 9 n s 81 tclcsl lcs_n active delay 0 9 ns 8 4 tl r l l lcs_n pre c ha rge pul s e wi dth t c l c l + tclch n s read c y cle timing resp onses 24 tazrl a d addre s s f l oat to rd_n active 0 ns 25 tclrl rd_n active delay 0 10 ns 26 trlrh rd_n pulse width tclcl ns 27 tclrh rd_n ina c tive delay 0 10 ns 2 8 t r h l h rd_n i n a c t i v e t o a l e h ig h tc l c h n s 59 trhdx rd_n h i g h t o d a t a h o l d o n a d b u s 0 n s 66 tavrl a a d d r e s s v a l i d t o rd_n l o w t c l c l + tchcl 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p s r a m w r i t e c y c l e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clkouta a19-a0 s6 ad15-ad0/ad7-ad0 ao15-ao8 ale wr_n whb_n/wlb_n/wb_n lcs_n address address s6 lock_n s6 s6 address data data address address 65 68 8 7 30 9 23 11 34 10 33 32 31 5 20 20 31 87 80 81 80 84 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p s r a m w r i t e c y c l e t i m i n g no. nam e com m ent min max units gener a l timing requir e ments 1 tdvcl data in setup 10 ns 2 tcldx data in hold 0 ns gener a l timing res pons es 5 t c l a v a d addre s s valid del ay 0 12 ns 7 tcldv data valid delay 0 12 ns 8 tchdx status hold t i me 0 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width tclch-5 ns 1 1 t c h l l a l e inactive delay null null ns 20 tcvctv control active delay 1 0 10 ns 2 3 tl h av a l e high to addre s s valid 7.5 ns 80 tclclx lcs_n i n a c t i v e d e l a y 0 9 n s 81 tclcsl lcs_n active delay 0 9 ns 8 4 tl r l l lcs_n pre c ha rge pul s e wi dth tclcl+ t c l c h n s write c y cle timing resp onses 30 tcldox data hold ti me 0 ns 31 tcvctx control inacti ve delay 0 10 ns 32 twlwh w r _ n p u l s e w i d t h 2 t c l c l n s 3 3 t w h l h w r _ n i n a c t i v e t o a l e h ig h tc l c h n s 34 twhdx data hold after w r _ n tclcl ns 65 tavwl a a d d r e s s v a l i d t o w r _ n l o w tclcl+ tchcl n s 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 8 7 t a v b l a a d d r e s s v a l i d t o w h b _ n / w l b _ n l o w tchcl - 1.5 n s 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p s r a m r e f r e s h c y c l e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clkouta a19-a0 ale rd_n lcs_n rfsh_n address address 9 11 10 26 28 27 27 80 81 25 79 82 86 85 p s r a m r e f r e s h c y c l e no. nam e com m ent min max units gener a l timing requir e ments 1 tdvcl data in setup 10 ns 2 tcldx data in hold 0 ns gener a l timing res pons es 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width tclch- 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s read/ w rite c y cle timing resp onse s 25 tclrl rd_n active delay 0 10 ns 26 trlrh rd_n pulse width tclcl ns 27 tclrh rd_n ina c tive delay 0 10 ns 2 8 t r h l h rd_n i n a c t i v e t o a l e h i g h t c l c h n s 80 tclclx lcs_n i n a c t i v e d e l a y 0 9 n s 81 tclcsl lcs_n active delay 0 9 ns refresh c y cle timing respons es 79 tchrfd c l k o u t a h i g h t o r f s h _ n va lid 0 12 ns 8 2 t c l r f c l k o u t a h i g h t o r f s h _ n invalid 0 12 ns 85 trfcy r f s h _ n c y c l e t i m e 6 t c l c l n s 8 6 t l c r f lcs_n i n a c t i v e t o r f s h _ n a c t i v e d e l a y 2 t c l c l n u l l n s 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i n t e r r u p t a c k n o w l e d g e c y c l e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160n s clkouta a19-a0 s6 ad15-ad0/ad7-ad0 ao15-ao8 ale bhe_n inta1_n/inta0_n den_n dt_r_n s2_n-s0_n address address s6 lock_n s6 s6 ptr address bhe_n bhe_n 68 7 8 12 1 2 9 23 15 10 11 4 31 20 22 19 22 22 21 3 4 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i n t e r r u p t a c k n o w l e d g e c y c l e t i m i n g no. nam e des c ription min max units gener a l timing requir e ments 1 tdvcl data in setup 10 ns 2 tcldx data in hold 0 ns gener a l timing res pons es 3 tchsv status active delay 0 6 ns 4 tclsh status inactiv e delay 0 6 ns 7 tcldv data valid delay 0 12 ns 8 tchdx status hold t i me 0 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width tclch- 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s 12 tavll a d a d d r e s s v a l i d t o a l e l o w t c l c h n s 15 tclaz a d addre s s f l oat delay 0 12 ns 19 tdxdl den_n i n a c t i v e t o d t _ r _ n l o w 0 n s 20 tcvctv control active delay 1 0 10 ns 2 1 tc vd ex den_n i n a c t i v e d e l a y 0 9 n s 22 tchctv control active delay 2 0 10 ns 2 3 tl h av a l e high to addre s s valid 7.5 ns 31 tcvctx control inacti ve delay 0 10 ns 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 software halt cycl e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns clkouta a19-a0 s6/ad[15:0/ad[8:0]/ao[15:8] ale den_n dt_r_n s2_n-s0_n invalid address invalid address invalid address invalid address status status 68 5 10 9 11 19 3 4 22 software halt cycl e timing no. nam e des c ription min max units gener a l timing res pons es 3 tchsv status active delay 0 6 ns 4 tclsh status inactiv e delay 0 6 ns 5 t c l a v a d addre s s valid del ay 0 12 ns 9 t c h l h a l e active de lay 0 8 ns 1 0 tl h l l a l e width tclch- 5 n s 1 1 t c h l l a l e in a c tiv e d e la y 0 8 n s 19 tdxdl den_n i n a c t i v e t o d t _ r _ n l o w 0 n s 22 tchctv control active delay 2 0 10 ns 68 tchav c l k o u t a h i g h t o a address valid 0 8 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 c l o c k C a c t i v e m o d e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns x2 x1 clkouta clkoutb 36 37 38 69 42 43 44 70 c l o c k C p o w e r - s a v e m o d e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns x2 x1 clkouta clkoutb(cbf=1) clkoutb(cbf=0) clock ti ming no. nam e des c ription min max units c l k i n r e q u i r e m e n t s 36 tckin x 1 p e rio d 2 5 6 6 n s 37 tclck x 1 low time 7.5 ns 38 tchck x 1 high time 7.5 ns 39 tckhl x 1 fall time 5 ns 4 0 t c k l h x 1 r i s e t i m e 5 n s c l k o u t t i m i n g 42 tclcl c l k o u t a p e r i o d 2 5 n s 43 tclch c l k o u t a lo w time tclcl/2 ns 44 tchcl c l k o u t a hig h time tclcl/2 ns 4 5 t c h 1 c h 2 c l k o u t a r i s e t i m e 3 n s 4 6 t c l 2 c l 1 c l k o u t a fall time 3 ns 61 tlock maximum pl l lock time 0.5 ms 69 tcicoa x 1 t o c l k o u t a s k e w 2 5 n s 70 tcicob x 1 t o c l k o u t b s k e w 3 5 n s 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 s r d y C s y n c h r o n o u s r e a d y 0ns 20ns 40ns 60ns 80ns 100ns 120ns clkouta srdy 47 48 a r d y - a s y n c h r o n o u s r e a d y 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140 clkouta ardy ardy ardy sytem normally not ready sytem normally ready system normally ready 49 49 50 50 51 52 periphera ls 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta int4-0/nmi/tmrin1-0 drq1-drq0 tmrout1-tmrout0 53 54 55 r e a d y a n d p e r i p h e r a l t i m i n g no. nam e des c ription min max units 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m ready and peripheral ti ming requir e ments 47 tsrycl srd y transition setup tim e 10 ns 48 tclsry srd y t r a n s i s t i o n h o l d t i m e 3 n s 4 9 ta r y c h ard y resoluti on tra n sitio n setup time 9 ns 50 tclarx ard y ac tiv e h o ld t ime 4 n s 51 tarychl ard y inactive holdi ng time 6 ns 52 tarylcl ard y setup time 9 ns 53 tinvch periph eral se tup time 10 ns 54 tinvcl drq setup ti me 10 ns peripheral timing respo nses 55 tcltmv timer o u tput delay 0 12 ns reset 1 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns x1 res_n clkouta low for n x1 cycles 57 57 reset 2 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 1 res_n clkouta aden_n/s6/clkdiv2,uzi_n ad[15:0],a0[15:8],ad[7:0] tri-state tri-state bhe_n/aden _n,rf sh2_n/
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m b u s h o l d e n t e r i n g 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta hold hlda ad[15:0],den_n s2_n-s1_n,whb_n,wlb_n 58 62 15 63 b u s h o l d l e a v i n g 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta hold hlda ad[15:0],den_n s2_n-s1_n,whb_n,wlb_n 58 62 5 64 r e s e t a n d b u s h o l d t i m i n g no. nam e des cription min max u nits res e t and bus hold timing requir ements 5 t c l a v a d addre s s valid del ay 0 12 ns 15 tclaz a d addre s s f l oat delay tclch ns 57 tresin r e s _ n setup time 10 ns 58 thvcl h l d setup time 10 ns res e t and bus hold timing res pons es 62 tclhav h l d a valid de lay 0 7 ns 63 tchcz comm and li nes flo at del ay 0 12 ns 64 tchcv comm and li nes valid del ay (after floa t) 0 12 ns a[19:0], s6,rd_ n, wr_n,bhe _n, dr /r _n a[19:0], s6,rd_ n, wr_n,bhe _n, dr /r _n
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 s y n c h r o n o u s s e r i a l in t e r f a c e 0ns 20ns 40ns 60ns 80ns 100ns 120ns 140ns clkouta sden sclk sdata(rx) sdata(tx) 71 72 75 78 77 data data s y n c h r o n o u s s e r i a l interface timing no. nam e des c ription min max units sy nchronou s serial port timing requ irements 75 tdvsh data valid to sclk h ig h 1 0 n s 77 tshdx sclk h i g h t o s p i d a t a h o l d 3 n s sy nchronou s serial port timing resp onses 7 1 tc l ev c l k o u t a l o w t o s d e n valid 0 12 ns 72 tclsl c l k o u t a l o w t o sclk l o w 0 1 2 n s 7 8 tsl d v sclk lo w to data valid 0 12 ns 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m i a 1 8 6 e m 1 0 0 - p i n p q f p h ld a a 7 a 5 a 0 a 8 a 6 a 4 whb_n gnd a 1 cc srdy h o l d dt/r_n n mi a 3 a 2 v wlb_n den_n m c s 0 ad8 dr q 0 _ n tm rin0 t m r o u t 1 res _ n mcs3 _ n/r f sh _ n v cc p c s 6 _ n/a2 ucs _ n/on ce1 _ n int1/selec t _ n int3/inta1 _ n / i r q mcs1 _ n p c s 2 _ n p c s 1 _ n v cc l c s _ n/onc e0 _ n ad1 ad0 dr q 1 _ n t m r o u t 0 tm rin1 g nd p c s 5 _ n/a1 n t0 int2/inta0 i _ n/ p w d in t4 mcs2 _ n g nd p c s 0 _ n s6 /clkdiv2_ n v cc a d 4 a d 1 3 a d 1 2 a d 3 uzi_n a d 1 5 a d 1 4 gnd a d 1 0 a d 9 sdata rxd t x d a d 7 a d 6 a d 5 a d 1 1 a d 2 p c s 3 _ n bhe _ n/ad s 1 en _ n clkouta g nd a 9 a 1 8 a 1 7 a 1 5 a 1 3 a 1 1 sden0 ard y g nd x 2 rd _ n sden1 sclk s 2 _ n s 0 _ n x 1 v cc clkoutb a 1 9 v cc a 1 6 a 1 4 a 1 2 a 1 0 w r ale _ n
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a186em 100-pin pq fp assignme nts ( s orted by p i n n umber) p i n # n a m e p i n # n a m e 1 s d e n 1 / p i o 2 3 5 1 m c s 1 _ n / p i o 1 5 2 s d e n 0 / p i o 2 2 5 2 i n t 4 / p i o 3 0 3 s c l k / p i o 2 0 5 3 i n t 3 / i n t a 1 _ n / i r q 4 b h e _ n / a d e n _ n 5 4 i n t 2 / i n t a 0 _ n / p i o 3 1 5 w r _n 55 int1/select_n 6 rd_n 56 int0 7 ale 57 ucs_n/once 1 _ n 8 a r d y 5 8 l c s _ n / o n c e 0 _ n 9 s 2 _ n 5 9 p c s 6 _ n / a 2 / p i o 2 1 0 s 1 _ n 6 0 p c s 5 _ n / a 1 / p i o 3 11 s0_n 61 v c c 1 2 g n d 6 2 p c s 3 _ n / p i o 1 9 1 3 x 1 6 3 p c s 2 _ n / p i o 1 8 1 4 x 2 6 4 g n d 1 5 v c c 6 5 p c s 1 _ n / p i o 1 7 1 6 c l k o u t a 6 6 p c s 0 _ n / p i o 1 6 17 clkoutb 67 v c c 1 8 g n d 6 8 m c s 2 _ n / p i o 2 4 1 9 a 1 9 / p i o 2 9 6 9 m c s 3 _ n / r f s h _ n / p i o 2 5 2 0 a 1 8 / p i o 8 7 0 g n d 2 1 v c c 71 res_n 2 2 a 1 7 / p i o 7 7 2 t m r i n 1 / p i o 2 5 2 3 a 1 6 7 3 t m r o u t 1 / p i o 1 2 4 a 1 5 7 4 t m r o u t 0 / p i o 1 0 25 a14 7 5 t m r i n 0 / p i o 1 1 2 6 a 1 3 7 6 d r q 1 / p i o 1 3 2 7 a 1 2 7 7 d r q 0 / p i o 1 2 2 8 a 1 1 7 8 a d 0 2 9 a 1 0 7 9 a d 8 3 0 a 9 8 0 a d 1 3 1 a 8 8 1 a d 9 3 2 a 7 8 2 a d 2 3 3 a 6 8 3 a d 1 0 34 a5 84 ad3 3 5 a 4 8 5 a d 1 1 3 6 a 3 8 6 a d 4 3 7 a 2 8 7 a d 1 2 3 8 v c c 8 8 a d 5 3 9 a 1 8 9 g n d 4 0 a 0 9 0 a d 1 3 4 1 g n d 9 1 a d 6 4 2 w h b _ n 9 2 v c c 4 3 w l b _ n 9 3 a d 1 4 4 4 h l d a 9 4 a d 7 4 5 h o l d 9 5 a d 1 5 46 srdy /pio6 96 s6/clkdiv2_n/pio29 4 7 n m i 9 7 u z i _ n / p i o 2 6 4 8 d t / r _ n / p i o 4 9 8 t x d / p i o 2 7 4 9 d e n _ n / p i o 5 9 9 r x d / p i o 2 8 5 0 m c s 0 _ n / p i o 1 4 1 0 0 s d a t a / p i o 2 1 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p i n n a m e n u m b e r p i n n a m e n u m b e r a 0 4 0 g n d 8 9 a 1 3 9 h l d a 4 4 a 2 3 7 h o l d 4 5 a 3 3 6 i n t 0 5 6 a 4 3 5 i n t 1 / s e l e c t _ n 5 5 a 5 3 4 i n t 2 / i n t a 0 _ n / p i o 3 1 5 4 a 6 3 3 i n t 3 / i n t a 1 _ n / i r q 5 3 a 7 3 2 i n t 4 / p i o 3 0 5 2 a 8 3 1 l c s _ n / o n c e 0 _ n 5 8 a 9 3 0 m c s 0 _ n / p i o 1 4 5 0 a 1 0 2 9 m c s 1 _ n / p i o 1 5 5 1 a 1 1 2 8 m c s 2 _ n / p i o 2 4 6 8 a 1 2 2 7 m c s 3 _ n / r f s h _ n / p i o 2 5 6 9 a 1 3 2 6 n m i 4 7 a 1 4 2 5 p c s 0 _ n / p i o 1 6 6 6 a 1 5 2 4 p c s 1 _ n / p i o 1 7 6 5 a 1 6 2 3 p c s 2 _ n / p i o 1 8 6 3 a 1 7 / p i o 7 2 2 p c s 3 _ n / p i o 1 9 6 2 a 1 8 / p i o 8 2 0 p c s 5 _ n / a 1 / p i o 3 6 0 a 1 9 / p i o 9 1 9 p c s 6 _ n / a 2 / p i o 2 5 9 a d 0 7 8 r d _ n 6 a d 1 8 0 r e s _ n 7 1 a d 2 8 2 r x d / p i o 2 8 9 9 a d 3 8 4 s 0 _ n 1 1 a d 4 8 6 s 1 _ n 1 0 a d 5 8 8 s 2 _ n 9 a d 6 9 1 s 6 / c l k d i v 2 / p i o 2 9 9 6 a d 7 9 4 s c l k / p i o 2 0 3 a d 8 7 9 s d a t a / p i o 2 1 1 0 0 a d 9 8 1 s d e n 0 / p i o 2 2 2 a d 1 0 8 3 s d e n 1 / p i o 2 3 1 a d 1 1 8 5 s r d y / p i o 6 4 6 a d 1 2 8 7 t m r i n 0 / p i o 1 1 7 5 a d 1 3 9 0 t m r i n 1 / p i o 0 7 2 a d 1 4 9 3 t m r o u t 0 / p i o 1 0 7 4 a d 1 5 9 5 t m r o u t 1 / p i o 1 7 3 a l e 7 t x d / p i o 2 7 9 8 a r d y 8 u c s _ n / o n c e 1 _ n 5 7 b h e _ n / a d e n _ n 4 u z i _ n / p i o 2 6 9 7 c l k o u t a 1 6 v c c 1 5 c l k o u t b 1 7 v c c 2 1 d e n _ n / p i o 5 4 9 v c c 3 8 d r q 0 / p i o 1 2 7 7 v c c 6 1 d r q 1 / p i o 1 3 7 6 v c c 6 7 d t / r _ n / p i o 4 4 8 v c c 9 2 g n d 1 2 w h b _ n 4 2 g n d 1 8 w l b _ n 4 3 g n d 4 1 w r _ n 5 g n d 6 4 x 1 1 3 g n d 7 0 x 2 1 4 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m i a 1 8 6 e m t q f p 1 0 0 - p i n lcs_n/on int0 gnd v c e0 _n pcs5_ cc n/a1 pcs2_ n a d 1 h o l d a d 8 a d 0 res_n int1/selec t_n pcs6_ n/a2 m c s 2 _ n t m r i n 0 drq0 drq1 tmr out0 tmr out1 t m r i n 1 gnd mcs 3_n/r fsh _n v cc pcs0_ n pcs1_ n ucs_n/on ce1 _n in t2 /in ta 0 _ n i n t 3 _ n / i n t a 1 _ n / i r q a d 7 v pcs3_ n cc a 1 3 v cc a d 3 a d 5 a d 1 3 a d 1 4 u z i _ n rxd sden1 s 6 / / c l k d i v 2 t x d sdata mcs1 _ n n m i den _ n int4 mcs0 _ n d t / r _ n srd y w l b _ n g nd a 0 v cc a 2 a 4 w h b _ n h l d a a 1 a 1 0 a 3 a 5 a 8 a 6 a 7 a 9 a 1 1 gnd a 1 7 rd_n x 2 wr_n a 1 8 clkoutb gnd a 1 5 ardy s 1 _ n a 1 4 a 1 9 x 1 s0 n s2 n ale bhe_n/ad e n_ n sclk a 1 2 a 1 6 v cc clkouta sden0 a d 1 5 a d 6 g nd a d 1 2 a d 4 a d 1 1 a d 1 0 a d 2 a d 9
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i a 1 8 6 e m 1 0 0 - p i n t q f p p i n a s s i g n m e n t s ( s o r t e d b y p i n n u m b e r ) p i n # n a m e p i n # n a m e 1 a d 0 5 1 a 1 1 2 a d 8 5 2 a 1 0 3 a d 1 5 3 a 9 4 a d 9 5 4 a 8 5 a d 2 5 5 a 7 6 a d 1 0 5 6 a 6 7 a d 3 5 7 a 5 8 a d 1 1 5 8 a 4 9 a d 4 5 9 a 3 1 0 a d 1 2 6 0 a 2 11 ad5 61 v c c 1 2 g n d 6 2 a 1 1 3 a d 1 3 6 3 a 0 1 4 a d 6 6 4 g n d 1 5 v c c 6 5 w h b _ n 1 6 a d 1 4 6 6 w l b _ n 1 7 a d 7 6 7 h l d a 1 8 a d 1 5 6 8 h o l d 19 s6/clkdiv2/pio29 69 srdy /pio6 2 0 u z i _ n / p i o 2 6 7 0 n m i 21 tx d 71 dt/r_n/ pio4 2 2 r x d 7 2 d e n _ n / p i o 5 2 3 s d a t a / p i o 2 1 7 3 m c s 0 _ n / p i o 1 4 2 4 s d e n 1 / p i o 2 3 7 4 m c s 1 _ n / p i o 1 5 2 5 s d e n 0 / p i o 2 2 7 5 i n t 4 / p i o 3 0 2 6 s c l k / p i o 2 0 7 6 i n t 3 / i n t a 1 _ n / i r q 2 7 b h e _ n / a d e n _ n 7 7 i n t 2 / i n t a 0 _ n / p i o 3 1 28 w r _n 78 int1/select_n 29 rd_n 79 int0 3 0 a l e 8 0 u c s _ n / o n c e 1 _ n 3 1 a r d y 8 1 l c s _ n / o n c e 0 _ n 3 2 s 2 _ n 8 2 p c s 6 _ n / a 2 / p i o 2 3 3 s 1 _ n 8 3 p c s 5 _ n / a 1 / p i o 3 34 s0_n 84 v c c 3 5 g n d 8 5 p c s 3 _ n / p i o 1 9 3 6 x 1 8 6 p c s 2 _ n / p i o 1 8 3 7 x 2 8 7 g n d 3 8 v c c 8 8 p c s 1 _ n / p i o 1 7 3 9 c l k o u t a 8 9 p c s 0 _ n / p i o 1 6 40 clkoutb 90 v c c 4 1 g n d 9 1 m c s 2 _ n / p i o 2 4 4 2 a 1 9 / p i o 9 9 2 m c s 3 _ n / r f s h _ n / p i o 2 5 4 3 a 1 8 / p i o 8 9 3 g n d 4 4 v c c 94 res_n 4 5 a 1 7 / p i o 7 9 5 t m r i n 1 / p i o 0 4 6 a 1 6 9 6 t m r o u t 1 / p i o 1 4 7 a 1 5 9 7 t m r o u t 0 / p i o 1 0 4 8 a 1 4 9 8 t m r i n 0 / p i o 1 1 4 9 a 1 3 9 9 d r q 1 / p i o 1 3 5 0 a 1 2 1 0 0 d r q 0 / p i o 1 2 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p i n n a m e n u m b e r p i n n a m e n u m b e r a 0 6 3 g n d 9 3 a 1 6 2 h l d a 6 7 a 2 6 0 h o l d 6 8 a 3 5 9 i n t 0 7 9 a 4 5 8 i n t 1 / s e l e c t _ n 7 8 a 5 5 7 i n t 2 / i n t a 0 _ n / p i o 3 1 7 7 a 6 5 6 i n t 3 / i n t a 1 _ n / i r q 7 6 a 7 5 5 i n t 4 / p i o 3 0 7 5 a 8 5 4 l c s _ n / o n c e 0 _ n 8 1 a 9 5 3 m c s 0 _ n / p i o 1 4 7 3 a 1 0 5 2 m c s 1 _ n / p i o 1 5 7 4 a 1 1 5 1 m c s 2 _ n / p i o 2 4 9 1 a 1 2 5 0 m c s 3 _ n / r f s h _ n / p i o 2 5 9 2 a 1 3 4 9 n m i 7 0 a 1 4 4 8 p c s 0 _ n / p i o 1 6 8 9 a 1 5 4 7 p c s 1 _ n p i o 8 8 a 1 6 4 6 p c s 2 _ n / p i o 1 8 8 6 a 1 7 / p i o 7 4 5 p c s 3 _ n / p i o 1 9 8 5 a 1 8 / p i o 8 4 3 p c s 5 _ n / a 1 / p i o 3 8 3 a 1 9 / p i o 9 4 2 p c s 6 _ n / a 2 / p i o 2 8 2 a d 0 1 r d _ n 2 9 a d 1 3 r e s _ n 9 4 a d 2 5 r x d / p i o 2 3 2 4 a d 3 7 s 0 _ n 3 4 a d 4 9 s 1 _ n 3 3 a d 5 1 1 s 2 _ n 3 2 a d 6 1 4 s 6 / c l k d i v 2 / p i o 2 9 1 9 a d 7 1 7 s c l k / p i o 2 0 2 6 a d 8 2 s d a t a / p i o 2 1 2 3 a d 9 4 s d e n 0 / p i o 2 2 2 5 a d 1 0 6 s d e n 1 / p i o 2 3 2 4 a d 1 1 8 s r d y / p i o 6 6 9 a d 1 2 1 0 t m r i n 0 / p i o 1 1 9 8 a d 1 3 1 3 t m r i n 1 / p i o 0 9 5 a d 1 4 1 6 t m r o u t 0 / p i o 1 0 9 7 a d 1 5 1 8 t m r o u t 1 / p i o 1 9 6 a l e 3 0 t x d / p i o 2 7 2 1 a r d y 3 0 u c s _ n / o n c e 1 _ n 8 0 b h e _ n / a d e n _ n 2 7 u z i _ n / p i o 2 6 2 0 c l k o u t a 3 9 v c c 1 5 c l k o u t b 4 0 v c c 3 8 d e n _ n / p i o 5 7 2 v c c 4 4 d r q 0 / p i o 1 2 1 0 0 v c c 6 1 d r q 1 / p i o 1 3 9 9 v c c 8 4 d t / r _ n / p i o 4 7 1 v c c 9 0 g n d 1 2 w h b _ n 6 5 g n d 3 6 w l b _ n 6 6 g n d 4 1 w r _ n 2 8 g n d 6 4 x 1 3 6 g n d 8 7 x 2 3 7 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m i a 1 8 8 e m 1 0 0 - p i n p q f p i a 1 8 8 e m 1 0 0 - p i n p q f p a 7 a 5 a 0 gnd h ld a ao8 dr q 0 tm rin0 t m r o u t 1 res_n mcs3 _ n/r f sh _ n v cc p c s 1 _ n p c s 2 _ n v cc p c s 6 _ n/a2 ucs _ n/on ce1 int1/selec t _ n int3/inta1 _ n / i r q ad1 ad0 dr q 1 t m r o u t 0 tm rin1 g nd mcs2 _ n p c s 0 _ n g nd sden0 rfsh2/a den _ n rd _ n ard y s 1 _ n g nd x 2 clkouta g nd a 1 8 a 1 7 a 1 5 a 1 3 a 1 1 sden1 sclk w r _ n ale s 2 _ n s 0 _ n x 1 v cc clkoutb a 1 9 v cc a 1 6 a 1 4 a 1 2 a 1 0 a 9 s6 /clkdiv2_ n v cc a d 4 a o 1 3 a o 1 2 a d 3 uzi_n a o 1 5 a o 1 4 gnd a o 1 0 a o 9 sdata rxd t x d a d 7 a d 6 a d 5 a o 1 1 a d 2 p c s 3 _ n p c s 5 _ n/a1 l c s _ n/onc e0 in t0 int2/inta0 _ n in t4 mcs1 _ n a 1 srdy dt/r_n a 8 a 6 a 4 a 3 a 2 v cc gnd wb_n h o l d n mi den_n m c s 0
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i a 1 8 8 e m 1 0 0 p i n p q f p a s s i g n m e n t s ( s o r t e d b y p i n n u m b e r ) p i n # n a m e p i n # n a m e 1 s d e n 1 / p i o 2 3 5 1 m c s 1 _ n / p i o 1 5 2 s d e n 0 / p i o 2 2 5 2 i n t 4 / p i o 3 0 3 s c l k / p i o 2 0 5 3 i n t 3 / i n t a 1 _ n / i r q 4 r f s h 2 _ n / a d e n _ n 5 4 i n t 2 / i n t a 0 _ n / p w d / p i o 3 1 5 w r _n 55 int1/select_n 6 rd_n 56 int0 7 ale 57 ucs_n/once 1 _ n 8 a r d y 5 8 l c s _ n / o n c e 0 _ n 9 s 2 _ n 5 9 p c s 6 _ n / a 2 / p i o 2 1 0 s 1 _ n 6 0 p c s 5 _ n / a 1 / p i o 3 11 s0_n 61 v c c 1 2 g n d 6 2 p c s 3 _ n / p i o 1 9 1 3 x 1 6 3 p c s 2 _ n / p i o 1 8 1 4 x 2 6 4 g n d 1 5 v c c 6 5 p c s 1 _ n / p i o 1 7 1 6 c l k o u t a 6 6 p c s 0 _ n / p i o 1 6 17 clkoutb 67 v c c 1 8 g n d 6 8 m c s 2 _ n / p i o 2 4 1 9 a 1 9 / p i o 2 9 6 9 m c s 3 _ n / r f s h _ n / p i o 2 5 2 0 a 1 8 / p i o 8 7 0 g n d 2 1 v c c 71 res_n 2 2 a 1 7 / p i o 7 7 2 t m r i n 1 / p i o 2 5 2 3 a 1 6 7 3 t m r o u t 1 / p i o 1 2 4 a 1 5 7 4 t m r o u t 0 / p i o 1 0 25 a14 7 5 t m r i n 0 / p i o 1 1 2 6 a 1 3 7 6 d r q 1 / p i o 1 3 2 7 a 1 2 7 7 d r q 0 / p i o 1 2 2 8 a 1 1 7 8 a d 0 2 9 a 1 0 7 9 a o 8 3 0 a 9 8 0 a d 1 3 1 a 8 8 1 a o 9 3 2 a 7 8 2 a d 2 3 3 a 6 8 3 a o 1 0 34 a5 84 ad3 3 5 a 4 8 5 a o 1 1 3 6 a 3 8 6 a d 4 3 7 a 2 8 7 a o 1 2 3 8 v c c 8 8 a d 5 3 9 a 1 8 9 g n d 4 0 a 0 9 0 a o 1 3 4 1 g n d 9 1 a d 6 42 gnd 92 v c c 43 w b _ n 93 ao14 4 4 h l d a 9 4 a d 7 4 5 h o l d 9 5 a o 1 5 46 srdy /pio6 96 s6/clkdiv2_n/pio29 4 7 n m i 9 7 u z i _ n / p i o 2 6 4 8 d t / r _ n / p i o 4 9 8 t x d / p i o 2 7 4 9 d e n _ n / p i o 5 9 9 r x d / p i o 2 8 5 0 m c s 0 _ n / p i o 1 4 1 0 0 s d a t a / p i o 2 1 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 p i n n a m e n u m b e r p i n n a m e n u m b e r a 0 4 0 g n d 8 9 a 1 3 9 h l d a 4 4 a 2 3 7 h o l d 4 5 a 3 3 6 i n t 0 5 6 a 4 3 5 i n t 1 / s e l e c t _ n 5 5 a 5 3 4 i n t 2 / i n t a 0 _ n / p w d / p i o 3 1 5 4 a 6 3 3 i n t 3 / i n t a 1 _ n / i r q 5 3 a 7 3 2 i n t 4 / p i o 3 0 5 2 a 8 3 1 l c s _ n / o n c e 0 _ n 5 8 a 9 3 0 m c s 0 _ n / p i o 1 4 5 0 a 1 0 2 9 m c s 1 _ n / p i o 1 5 5 1 a 1 1 2 8 m c s 2 _ n / p i o 2 4 6 8 a 1 2 2 7 m c s 3 _ n / r f s h _ n / p i o 2 5 6 9 a 1 3 2 6 n m i 4 7 a 1 4 2 5 p c s 0 _ n / p i o 1 6 6 6 a 1 5 2 4 p c s 1 _ n / p i o 1 7 6 5 a 1 6 2 3 p c s 2 _ n / c t s 1 _ n / e n r x 1 _ n / p i o 1 8 6 3 a 1 7 / p i o 7 2 2 p c s 3 _ n / r t s 1 _ n / r t r 1 _ n / p i o 1 9 6 2 a 1 8 / p i o 8 2 0 p c s 5 _ n / a 1 / p i o 3 6 0 a 1 9 / p i o 9 1 9 p c s 6 _ n / a 2 / p i o 2 5 9 a d 0 7 8 r d _ n 6 a d 1 8 0 r e s _ n 7 1 a d 2 8 2 r f s h 2 _ n / a d e n _ n 4 a d 3 8 4 r x d / p i o 2 8 9 9 a d 4 8 6 s 0 _ n 1 1 a d 5 8 8 s 1 _ n 1 0 a d 6 9 1 s 2 _ n 9 a d 7 9 4 s 6 / l o c k _ n / c l k d i v 2 / p i o 2 9 9 6 a l e 7 s c l k / p i o 2 0 3 a o 8 7 9 s d a t a / p i o 2 1 1 0 0 a o 9 8 1 s d e n 0 / p i o 2 2 2 a o 1 0 8 3 s d e n 1 / p i o 2 3 1 a o 1 1 8 5 s r d y / p i o 6 4 6 a o 1 2 8 7 t m r i n 0 / p i o 1 1 7 5 a o 1 3 9 0 t m r i n 1 / p i o 0 7 2 a o 1 4 9 3 t m r o u t 0 / p i o 1 0 7 4 a o 1 5 9 5 t m r o u t 1 / p i o 1 7 3 a r d y 8 t x d / p i o 2 7 9 8 c l k o u t a 1 6 u c s _ n / o n c e 1 _ n 5 7 c l k o u t b 1 7 u z i _ n / p i o 2 6 9 7 d e n _ n / d s _ n / p i o 5 4 9 v c c 1 5 d r q 0 / p i o 1 2 7 7 v c c 2 1 d r q 1 / p i o 1 3 7 6 v c c 3 8 d t / r _ n / p i o 4 4 8 v c c 6 1 g n d 1 2 v c c 6 7 g n d 1 8 v c c 9 2 g n d 4 1 w b _ n 4 2 g n d 4 2 w r _ n 5 g n d 6 4 x 1 1 3 g n d 7 0 x 2 1 4 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m i a 1 8 8 e m 1 0 0 - p i n t q f p i a 1 8 8 e m 1 0 0 - p i n t q f p int1/selec t_n mcs1 _ n n m i lcs_n/onc e0 _n x 2 a 1 5 x 1 rd_n a 1 6 clkoutb gnd v cc int4 mcs0 a 1 8 gnd v cc a 1 4 a 1 7 a 1 9 ardy s 1 _ n s 2 _ n s 0 _ n ale rfsh2/a d wr_n en_ n sclk a 1 2 _ n den _ n d t / r _ n srd y h o l d w b _ n g nd h l d a a 1 g nd a 0 v cc a 2 a 4 a 3 a 5 a 1 0 a 8 a 6 a 7 a 9 a 1 1 a 1 3 clkouta res_n pcs5_ n/a1 pcs6_ n/a2 int0 m c s 2 _ n t m r i n 0 drq0 drq1 tmr out0 tmr out1 t m r i n 1 gnd mcs 3_n/r fsh _n v cc pcs0_ n pcs1_ n gnd pcs2_ n pcs3_ n v cc in t2 /in ta 0 _ n i n t 3 _ n / i n t a 1 _ n / i r q a o 8 a o 9 a o 1 0 a o 1 1 a o 1 2 ucs_n/on ce1 _n g nd a d 6 a o 1 4 a o 1 5 u z i _ n rxd sden1 a d 0 a d 1 a d 2 a d 3 a d 4 a d 5 a o 1 3 v cc a d 7 s 6 / / c l o c k d i v 2 t x d sdata sden0
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 i a 1 8 8 e m 1 0 0 - p i n t q f p p i n a s s i g n m e n t s ( s o r t e d b y p i n n u m b e r ) p i n # n a m e p i n # n a m e 1 a d 0 5 1 a 1 1 2 a o 8 5 2 a 1 0 3 a d 1 5 3 a 9 4 a o 9 5 4 a 8 5 a d 2 5 5 a 7 6 a o 1 0 5 6 a 6 7 a d 3 5 7 a 5 8 a o 1 1 5 8 a 4 9 a d 4 5 9 a 3 1 0 a o 1 2 6 0 a 2 11 ad5 61 v c c 1 2 g n d 6 2 a 1 1 3 a o 1 3 6 3 a 0 1 4 a d 6 6 4 g n d 1 5 v c c 6 5 g n d 1 6 a o 1 4 6 6 w b _ n 1 7 a d 7 6 7 h l d a 1 8 a o 1 5 6 8 h o l d 19 s6/clkdiv2/pio29 69 srdy /pio6 2 0 u z i _ n / p i o 2 6 7 0 n m i 2 1 t x d / p i o 2 7 7 1 d t / r _ n / p i o 4 2 2 r x d / p i o 2 8 7 2 d e n _ n / p i o 5 2 3 s d a t a / p i o 2 1 7 3 m c s 0 _ n / p i o 1 4 2 4 s d e n 1 / p i o 2 3 7 4 m c s 1 _ n / p i o 1 5 2 5 s d e n 0 / p i o 2 2 7 5 i n t 4 / p i o 3 0 2 6 s c l k / p i o 2 0 7 6 i n t 3 / i n t a 1 _ n / i r q 2 7 r f s h 2 _ n / a d e n _ n 7 7 i n t 2 / i n t a 0 _ n / p i o 3 1 28 w r _n 78 int1/select_n 29 rd_n 79 int0 3 0 a l e 8 0 u c s _ n / o n c e 1 _ n 3 1 a r d y 8 1 l c s _ n / o n c e 0 _ n 3 2 s 2 _ n 8 2 p c s 6 _ n / a 2 / p i o 2 3 3 s 1 _ n 8 3 p c s 5 _ n / a 1 / p i o 3 34 s0_n 84 v c c 3 5 g n d 8 5 p c s 3 _ n / p i o 1 9 3 6 x 1 8 6 p c s 2 _ n / p i o 1 8 3 7 x 2 8 7 g n d 3 8 v c c 8 8 p c s 1 _ n / p i o 1 7 3 9 c l k o u t a 8 9 p c s 0 _ n / p i o 1 6 40 clkoutb 90 v c c 4 1 g n d 9 1 m c s 2 _ n / p i o 2 4 4 2 a 1 9 / p i o 9 9 2 m c s 3 _ n / r f s h _ n / p i o 2 5 4 3 a 1 8 / p i o 8 9 3 g n d 4 4 v c c 94 res_n 4 5 a 1 7 / p i o 7 9 5 t m r i n 1 / p i o 0 4 6 a 1 6 9 6 t m r o u t 1 / p i o 1 4 7 a 1 5 9 7 t m r o u t 0 / p i o 1 0 4 8 a 1 4 9 8 t m r i n 0 / p i o 1 1 4 9 a 1 3 9 9 d r q 1 / p i o 1 3 5 0 a 1 2 1 0 0 d r q 0 / p i o 1 2 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 pin nam e num ber pin nam e num ber a 0 6 3 g n d 9 3 a 1 6 2 h l d a 6 7 a 2 6 0 h o l d 6 8 a 3 5 9 i n t 0 7 9 a 4 5 8 i n t 1 / s e l e c t _ n 7 8 a 5 5 7 i n t 2 / i n t a 0 _ n / p i o 3 1 7 7 a 6 5 6 i n t 3 / i n t a 1 _ n / i r q 7 6 a 7 5 5 i n t 4 / p i o 3 0 7 5 a 8 5 4 l c s _ n / o n c e 0 _ n 8 1 a 9 5 3 m c s 0 _ n / p i o 1 4 7 3 a 1 0 5 2 m c s 1 _ n / p i o 1 5 7 4 a 1 1 5 1 m c s 2 _ n / p i o 2 4 9 1 a 1 2 5 0 m c s 3 _ n / r f s h _ n / p i o 2 5 9 2 a 1 3 4 9 n m i 7 0 a 1 4 4 8 p c s 0 _ n / p i o 1 6 8 9 a 1 5 4 7 p c s 1 _ n / p i o 1 7 8 8 a 1 6 4 6 p c s 2 _ n / p i o 1 8 8 6 a 1 7 / p i o 7 4 5 p c s 3 _ n / p i o 1 9 8 5 a 1 8 / p i o 8 4 3 p c s 5 _ n / a 1 / p i o 3 8 3 a 1 9 / p i o 9 4 2 p c s 6 _ n / a 2 / p i o 2 8 2 a l e 3 0 r d _ n 2 9 a d 0 1 r e s _ n 9 4 a d 1 3 r f s h 2 _ n / a d e n _ n 2 7 a d 2 5 r x d / p i o 2 8 2 2 a d 3 7 s 0 _ n 3 4 a d 4 9 s 1 _ n 3 3 a d 5 1 1 s 2 _ n 3 2 a d 6 1 4 s 6 / l o c k _ n / c l k d i v 2 / p i o 2 9 1 9 a d 7 1 7 s c l k / p i o 2 0 2 6 a o 8 2 s d a t a / p i o 2 1 2 3 a o 9 4 s d e n 0 / p i o 2 2 2 5 a o 1 0 6 s d e n 1 / p i o 2 3 2 4 a o 1 1 8 s r d y / p i o 6 6 9 a o 1 2 1 0 t m r i n 0 / p i o 1 1 9 8 a o 1 3 1 3 t m r i n 1 / p i o 0 9 5 a o 1 4 1 6 t m r o u t 0 / p i o 1 0 9 7 a o 1 5 1 8 t m r o u t 1 / p i o 1 9 6 a r d y 3 0 t x d / p i o 2 7 2 1 c l k o u t a 3 9 u c s _ n / o n c e 1 _ n 8 0 c l k o u t b 4 0 u z i _ n / p i o 2 6 2 0 d e n _ / p i o 5 7 2 v c c 1 5 d r q 0 / p i o 1 2 1 0 0 v c c 3 8 d r q 1 / p i o 1 3 9 9 v c c 4 4 d t / r _ n / p i o 4 7 1 v c c 6 1 g n d 1 2 v c c 8 4 g n d 3 5 v c c 9 0 g n d 4 1 w b _ n 6 6 g n d 6 4 w r _ n 2 8 g n d 6 5 x 1 3 6 g n d 8 7 x 2 3 7 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m ph y s ical dimensi ons pqfp 100 p l a t i n g pin 1 indicator
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 d i m e n s i o n s i n i n c h e s d i m e n s i o n s i n m m s y mb o l minimum nominal maximum mi nimum nominal maximum a - - - - - - - - 0 . 1 3 4 - - - - - - - - 3 . 4 0 a 1 0 . 0 1 0 - - - - - - - - 0 . 2 5 - - - - - - - - a 2 0 . 1 0 7 0 . 1 1 2 0 . 1 1 7 2 . 7 3 2 . 8 5 2 . 9 7 b 0 . 0 1 0 0 . 0 1 2 0 . 0 1 5 0 . 2 5 0 . 3 0 0 . 3 8 b 1 0 . 0 0 9 0 . 0 1 2 0 . 0 1 3 0 . 2 2 0 . 3 0 0 . 3 3 c 0 . 0 0 5 0 . 0 0 6 0 . 0 0 9 0 . 1 3 0 . 1 5 0 . 2 3 c 1 0 . 0 0 4 0 . 0 0 6 0 . 0 0 7 0 . 1 1 0 . 1 5 0 . 1 7 d 0 . 9 0 6 0 . 9 1 3 0 . 9 2 1 2 3 . 0 0 2 3 . 2 0 2 3 . 4 0 d 1 0 . 7 8 3 0 . 7 8 7 0 . 7 9 1 1 9 . 9 0 2 0 . 0 0 2 0 . 1 0 e 0 . 6 6 9 0 . 6 7 7 0 . 6 8 5 1 7 . 0 0 1 7 . 2 0 1 7 . 4 0 e 1 0 . 5 4 7 0 . 5 5 1 0 . 5 5 5 1 3 . 9 0 1 4 . 0 0 1 4 . 1 0 0 . 0 2 6 b s c 0 . 6 5 b s c l 0 . 0 2 9 0 . 0 3 5 0 . 0 4 1 0 . 7 3 0 . 8 8 1 . 0 3 l 1 0 . 0 6 3 b s c 1 . 6 0 b s c r 1 0 . 0 0 5 - - - - - - - - 0 . 1 3 - - - - - - - - r 2 0 . 0 0 5 - - - - 0 . 0 1 2 0 . 1 3 - - - - 0 . 3 0 s 0 . 0 0 8 - - - - - - - - 0 . 2 0 - - - - - - - - y - - - - - - - - 0 . 0 0 4 - - - - - - - - 0 . 1 0 ) 0 % - - - - 7 % 0 % - - - - 7 % ) 1 0 % - - - - - - - - 0 % - - - - - - - - ) 2 9 % 1 0 % 1 1 % 9 % 1 0 % 1 1 % ) 3 9 % 1 0 % 1 1 % 9 % 1 0 % 1 1 % e n o t e s 1. di m e nsions d 1 and e 1 do not include m old protrusion. bu t m o l d m i s m a t c h i s i n c l u d e d . allowable p r otrusi on is 0.25mm /0.010 * p e r s i d e . 2. di m e nsion b does not include dambar prot rusion. allowable protrusion is 0.08mm/0.003 * total i n e x c e s s o f t h e b d i m e n s i o n a t m a x i m u m m a t e r i al condition. da m bar cannot be located on the lower radius or the foot. 3. c o n t r o l l i n g d i m e n s i o n : m i l l i m e t e r . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m t q f p 1 0 0 d i m e n s i o n s i n m m d i m e n s i o n s i n i n c h e s s y mb o l minimum nominal maximum m inimum nominal maximum b 0 . 1 7 0 . 2 0 0 . 2 7 0 . 0 0 7 0 . 0 0 8 0 . 0 1 1 e 0 . 5 0 b s c 0 . 0 2 b s c d 2 1 2 . 0 0 0 . 4 7 2 e 2 1 2 . 0 0 0 . 4 7 2 a a a 0 . 2 0 0 . 0 0 8 b b b 0 . 2 0 0 . 0 0 8 c c c 0 . 0 8 0 . 0 0 3 d d d 0 . 0 8 0 . 0 0 3 p i n 1 i n d i c a t o r
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 o r d e r i n g i n f o r m a t i o n i n n o v a s i c # part n um b er amd # part n u m b er p a c k a g e t y p e t em perat u re grades i a 1 8 6 e m - p q f 1 0 0 i ( s t a n d a r d p a c k a g i n g ) a m 1 8 6 e m - 2 0 k c \ w a m 1 8 6 e m - 2 0 k i \ w a m 1 8 6 e m - 2 5 k c \ w a m 1 8 6 e m - 2 5 k i \ w a m 1 8 6 e m - 3 3 k c \ w a m 1 8 6 e m - 4 0 k c \ w 1 0 0 - p i n p l a s t i c q u a d flat package (pqfp) co mmercial and i n d u s t r i a l i a 1 8 6 e m - p q f 1 0 0 i - r ( r o h s p a c k a g i n g ) a m 1 8 6 e m - 2 0 k c \ w a m 1 8 6 e m - 2 0 k i \ w a m 1 8 6 e m - 2 5 k c \ w a m 1 8 6 e m - 2 5 k i \ w a m 1 8 6 e m - 3 3 k c \ w a m 1 8 6 e m - 4 0 k c \ w i a 1 8 6 e m - p t q 1 0 0 i ( s t a n d a r d p a c k a g i n g ) a m 1 8 6 e m - 2 0 v c \ w a m 1 8 6 e m - 2 5 v c \ w a m 1 8 6 e m - 3 3 v c \ w a m 1 8 6 e m - 4 0 v c \ w 1 0 0 - p i n t h i n q u a d f l a t package (tq fp) co mmercial and i n d u s t r i a l i a 1 8 6 e m - p t q 1 0 0 i - r ( r o h s p a c k a g i n g ) a m 1 8 6 e m - 2 0 v c \ w a m 1 8 6 e m - 2 5 v c \ w a m 1 8 6 e m - 3 3 v c \ w a m 1 8 6 e m - 4 0 v c \ w i a 1 8 8 e m - p q f 1 0 0 i ( s t a n d a r d p a c k a g i n g ) a m 1 8 8 e m - 2 0 k c \ w a m 1 8 8 e m - 2 0 k i \ w a m 1 8 8 e m - 2 5 k c \ w a m 1 8 8 e m - 2 5 k i \ w a m 1 8 8 e m - 3 3 k c \ w a m 1 8 8 e m - 4 0 k c \ w 1 0 0 - p i n p l a s t i c q u a d flat package (pqfp) co mmercial and i n d u s t r i a l i a 1 8 8 e m - p q f 1 0 0 i - r ( r o h s p a c k a g i n g ) a m 1 8 8 e m - 2 0 k c \ w a m 1 8 8 e m - 2 0 k i \ w a m 1 8 8 e m - 2 5 k c \ w a m 1 8 8 e m - 2 5 k i \ w a m 1 8 8 e m - 3 3 k c \ w a m 1 8 8 e m - 4 0 k c \ w i a 1 8 8 e m - p t q 1 0 0 i ( s t a n d a r d p a c k a g i n g ) a m 1 8 8 e m - 2 0 v c \ w a m 1 8 8 e m - 2 5 v c \ w a m 1 8 8 e m - 3 3 v c \ w a m 1 8 8 e m - 4 0 v c \ w 1 0 0 - p i n t h i n q u a d f l a t package (tq fp) co mmercial and i n d u s t r i a l i a 1 8 8 e m - p t q 1 0 0 i - r ( r o h s p a c k a g i n g ) a m 1 8 8 e m - 2 0 v c \ w a m 1 8 8 e m - 2 5 v c \ w a m 1 8 8 e m - 3 3 v c \ w a m 1 8 8 e m - 4 0 v c \ w other packages and te m p er ature grades may be ava i l a b l e f o r a n a d d i t i o n a l c o s t a n d l e a d t i m e . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 errata v e r s i o n - 0 1 1 ) p r o b l e m : m c s c h i p s e l e c t s i g n a l s ( m c s 0 - 3 ) a r e i n t e r m i t t e ntly suppressed. all other signals in bus c y cle a p p e a r c o r r e c t ( i . e . a d d r e s s , d a t a , w r i t e / r e a d s t r o b e s ) . a n a l y s i s : anomaly occurs when an acc ess to i/o spa ce is i mmedia t ely followed by an mcs a cces s. given the w a y i n s t r u c t i o n p r e f e t c h e s n a t u r a l l y s e p a r a t e s u c h a c c e s s e s , o n e k n o w n s c e n a r i o for this anomaly is via a dma s e q u e n c e . p o s s i b l e c o m b i n a t i o n s a r e : ( 1 ) d m a w r i t e t o d e s t i n a t i o n i s f o l l o w e d b y p r e v i o u s l y s c h e d u l e d m cs read or write, (2) dm a fro m i/ o space to m c s space. custom ers using the uart dma fe ature of the es pr oducts m a y be particularly sensitive to this, because whe n the tx data regis t e r of the pcb i s i n i / o s p a c e , e v e n t u a l l y a n m c s a c c e s s w i l l b e corrupted. another known scenario occurs when auxiliary fl ash (containing executable code) is selected by an mcs signal and the pcb or pc s selects are in i/o space. the pcb register block and the pc s address sp aces are the o nly areas that can be assigned to i/o space. the pcb register block is co nfigured by bit 12 of the relr eg, and defaults to i/o space. pcs space is configured by bit 6 of the mpcs , and m ust be initialized by the user. w o r k a r o u n d : i f p o s s i b l e , a s s i g n p c b a n d p c s a d d r e s s l o c a t i ons to me m o ry spac e instead of i/o space. 2 ) p r o b l e m : i a 1 8 6 e s d e v i c e s d o n o t w o r k i n a 1 8 8 e s s o c k e t . a n a l y s i s : t h e w h b p i n s h o u l d b e s a m p l e d a t r e s e t t o configure the bus width. this pin is always grounded in 188 applications, and floats high during re set in 186 applications. the bus width of the innovasic devices are confi g u re d v i a i n -p a c k a g e b o n d i n g . w o r k a r o u n d : u s e i a 1 8 8 e s d e v i c e s f o r 1 8 8 s o c k e t s . 3 ) p r o b l e m : n o i s e o n t m r o u t 0 ( p i o 1 0 ) a n d t m r o u t 1 ( p i o 1 ) w h e n i n p i o o u t p u t m o d e . a n a l y s i s : o nly occurs w hen application is using hold/hlda function, and either t m rout pi n is in pio output m ode. i m proper logic allows the tmr out pi n to tri-state when hlda is asserted. analysis shows that uzi (pio26), s 6clk2 (pio29) , den (pio5), and dt_r (pio4) m a y also be affected. pio input m odes and norma l operation modes are not affected. w o r k a r o u n d : i f p o s s i b l e , u s e a p i o p i n o t h e r t h a n t h o s e l i s t e d a b o v e w h e n u t i l i z i n g h o l d / h l d a f e a t u r e . a n e x t e r n a l p u l l u p / p u l l d o w n m a y a l s o h e l p . 4 ) p r o b l e m : an extra dma c y cle occurs after ending d m a transfers via a dma c ontrol registe r write. in certain applications, this extra dma cy cle occurrence w i l l h a n g t h e d e v i c e b e c a u s e o f d r e q / s r d y d e p e n d e n c y . 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 a n a l y s i s : t he string of dma transfers is ended by writing x0004 to pcb address xca or xda while dma request line is asserted. by this tim e, th e sequence to initiate the dma transfer cannot be suppressed or recalled, so the ia de vice executes the spurious transfer. w o r k a r o u n d : n o n e . 5 ) p r o b l e m : i n t h e 1 8 6 / 1 8 8 e s d e v i c e s , t h e t b 8 b i t o f t h e u a r t c o n t r o l r e g i s t e r ( o f f s e t x 1 0 o r x 8 0 ) d o e s n o t a u t o m a t i c a l l y r e s e t a f t e r t r a n s m i t t i n g t h e i n i t i a l w o r d w h e n u s i n g 9 - b i t f o r m a t s ( m o d e s 2 o r 3 ) . a n a l y s i s : t his feature is used to designate the ?ddress?byte wh en using the uart in a psuedo- lan configuration. the autom a tic reset of tb8 a l l o w s a c o n v e n i e n t m e a n s t o s e n d a b l o c k o f w o rd s with little soft ware interaction. w o r k a r o u n d : m anually reset tb8 after detecting t h e e n d o f t h e f i r s t t r a n s m i t t e d w o r d . 6 ) p r o b l e m : i n t h e 1 8 6 / 1 8 8 e s d e v i c e s , t h e p o w e r s a v e c l o c k s p e e d i s n o t w o r k i n g c o r r e c t l y . a n a l y s i s : a l o g i c e r r o r c a u s e s t h e d e v i c e t o i n c o r r e c tly c l ea r bits [ 2:0] of the pdcon when the device leaves power save m ode by c l earing bit 15 of the pdcon. w o r k a r o u n d : e v e r y t i m e t h e p r o g r a m m e r d e s i r e s t o g o i n t o p o w e r s a v e m o d e b y s e t t i n g b i t 1 5 o f t h e p d c o n r e g i s t e r , t h e n b i t s [ 2 : 0 ] s h o u l d a l s o b e s e t a c c o r d i n g t o t h e d e s i r e d c l o c k d i v i d e f a c t o r . i t s h o u l d n o t b e a s s u m e d t h a t o n c e w r i t t e n t o , b i t s [ 2 : 0 ] w i l l r e t a i n t h e i r v a l u e s w h e n e n t e r i n g a n d e x i t i n g t h e p o w e r s a v e m o d e . 7 ) p r o b l e m : the device resp onds incorrectly to false start bits. a n a l y s i s : if a start bit is less than half width, the device should ignor e t h i s s t a r t b i t c o m p l e t e l y ( n o d a t a b y t e , n o e r r o r s ) . i n s t e a d t h e d e v i c e t r e a t s t h e data that follows as a valid byte, and generates a f r a m i n g e r r o r . w o r k a r o u n d : elim inat e fal se start bits, or revise how the resulting fra m ing error and extra by te are handled. 8 ) p r o b l e m : t h e u a r t i s d i s a b l e d w h e n a n e x t e r n a l s y s t e m g e n e r a t e s a b r e a k c o n d i t i o n . a n a l y s i s : t he device should not be disabled when an external system ge nerates a break condition, instead once the break condition is d e a s s e r t e d t h e u a r t s h o u l d s t a r t r e c e i v i n g d a t a . h o w e v e r , t h e u a rt i n t h e in n o v a s i c d e v i c e i s d i sabled by the externally genera ted break condition and can only receive data once the b r eak flags (bit 9: brk0 of registers sp 0st and/ o r s p 1 s t ) a re c l e a re d . w o r k a r o u n d : e n s u r e t h a t e v e r y t i m e a n e x t e r n a l b r e a k c o n d i t i o n i s a c k n o w l e d g e d , t h a t t h e b r e a k f l a g b i t s a r e cleared. 9 ) p r o b l e m : t h e m o v i n s t r u c t i o n d o e s w o r k w h e n a n a t t e m p t i s m a d e t o l o a d t h e c s r e g i s t e r . a n a l y s i s : on the oem amd part a mov cs, ax co mm an d l o a d s c s w i t h t h e c o n t e n t s o f a x . t h e innovasic part never loads cs with ax by use of a mov instruction. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 w o r k a r o u n d : to load the cs register use a far jmp co mmand. 1 0 ) p r o b l e m : there is a differ e nce in how priority of timer interrupts are ass erted be tween the original am d part and the innovasic part. a n a l y s i s : i n t h e o r i g i n a l a m d p a r t , t i m e r i n t e r r u p t s cannot be interrupted by a n o t h e r t i m e r i n t e r r u p t , e v e n i f t h e n e w t i m e r i n t e r r u p t i s o f a h i g h e r p r i o r i t y . t h e i n n o v a s i c p a r t w i l l i n t e r r u p t a t i m e r i n t e r r u p t w i t h a h i g h e r p r i o r i t y t i m e r i n t e r r u p t . a d d i t i o n a l l y , i f a l o w e r p r i o r i t y t i m e r i n t e r r u p t i s i n t e r r u p t e d w i t h a h i g h e r p r i o r i t y t i m e r i n t e r r u p t a n d a n o t h e r o c c u r r e n c e o f t h e l o w e r p r i o r i t y i n t e r r u p t occurs during the processing of the higher priority interrupt, upon execution of the eoi a new lower p r i o r i t y i n t e r r u p t w i l l b e i n i t iated, possibly orphaning the original l o w e r p r i o r i t y t i m e r i n t e r r u p t . w o r k a r o u n d : w h e n u s i n g n e s t e d i n t e r r u p t s , a t t h e b e g i n n i n g o f t h e i n t e r r u p t r o u t i n e b e f o r e t h e g l o b a l interrupts are enabled with a cli, ti m e r i n terrupts m u s t be specifical ly m a sked. at the end of the ti m e r i n t e r r u p t r o u t i n e b e i n g s e r v i c e d , y o u n e e d t o s e t t h e i n t e r r u p t e n a b l e b i t i n t h e p r o c e s s s t a t u s w o r d t o g l o b a l l y d i s a b l e i n t e r r u p t s p r i o r t o c l e a r i n g t h e t i m e r i n t e r r u p t b e i n g s e r v i c e d . 1 1 ) p r o b l e m : u a r t w i l l n o t r e s p o n d t o b r e a k c o n d i t i o n i f r x d i s l o w w h e n r e c e i v e r i s e n a b l e d . a n a l y s i s : d e tection of a break only occurs with a fa l l i n g e d g e o f r x d w h i l e r e c e i v e r i s e n a b l e d . w o r k a r o u n d : n o n e . 1 2 ) p r o b l e m : u a r t t r a n s m i t t e r w i l l n o t s t a r t i f t x i n t e r r u p t c o n d i t i o n s e x i s t p r i o r t o e n a b l i n g t r a n s m i t t e r . a n a l y s i s : p r iority of logic design inadvert ently causes this lock up condition . w o r k a r o u n d : n e e d t o h a v e t r a n s m i t t e r e n a b l e d p r i o r t o a n y expected data transfers, or clear an y spurious i n t e r r u p t s b e f o r e e n a b l i n g . 1 3 ) p r o b l e m : lock up just after reset is r e le ased. a n a l y s i s : u s u a l l y , t h e f i r s t i n s t r u ction is a long jum p to the start of the user' s code. in this case, the c o m p i l e r a p p a re n t l y i n s e rt e d a s h o rt j u m p i n s t ru c t i on with zero displacem e nt before the expected long j u m p i n s t ru c t i o n . t h e o e m d e v i c e s t u t t e re d , b u t r ecovered to execute the l o n g j u m p , w h i l e t h e i a device instruction pointer was corrupted, causing th e lock up. in summary, a short jum p with zero d i s p l a c e m e n t i s a c o r n e r c a s e t h a t does not work in the ia device. w o r k a r o u n d : d o n o t u s e a s h o r t j u m p i n s t r u c t i o n w i t h z e r o d i s p l a c e m e n t . 1 4 ) p r o b l e m : i n t e r m i t t e n t s t a r t u p . a n a l y s i s : p r o c e s s o r e i t h e r c a m e o u t of reset norm a lly, or would go into a series of watchdog tim eouts. the addition of 10k oh m pullups to the w r _n an d r d _ n o u t p u t s s e e m e d t o s o l v e t h e i s s u e . further analysis of the oem device shows the presence of undocum ented pullups on these pins, 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 w h i c h w i l l p u l l t h e m h i g h w h e n t h e r e s e t c o n d i t i o n t r i s t a t e s t h e s e p i n s . t h e innovasic device does not include internal pullups on these pins allo wing these outputs to float during reset. w o r k a r o u n d : a d d 1 0 k o h m p u l l u p s t o w r _ n a n d r d _ n p i n s t o guarantee proper logic levels at the end of reset. v e r s i o n - 0 3 1 ) p r o b l e m : there is a differ e nce in how priority of timer interrupts are ass erted be tween the original am d part and the innovasic part. a n a l y s i s : i n t h e o r i g i n a l a m d p a r t , t i m e r i n t e r r u p t s c a n n o t b e i n t e r r u p t e d b y a n o t h e r t i m e r i n t e r r u p t , e v e n i f t h e n e w t i m e r i n t e r r u p t i s o f a h i g h e r p r i o r i t y . t h e i n n o v a s i c p a r t w i l l i n t e r r u p t a t i m e r i n t e r r u p t w i t h a h i g h e r p r i o r i t y t i m e r i n t e r r u p t . a d d i t i o n a l l y , i f a l o w e r p r i o r i t y t i m e r i n t e r r u p t i s i n t e r r u p t e d w i t h a h i g h e r p r i o r i t y t i m e r i n t e r r u p t a n d a n o t h e r o c c u r r e n c e o f t h e l o w e r p r i o r i t y i n t e r r u p t o c c u r s d u r i n g t h e p r o c e s s i n g o f t h e h i g h e r p r i o r i t y i n t e r r u p t , u p o n e x e c u t i o n o f t h e e o i a n e w l o w e r p r i o r i t y i n t e r r u p t w i l l b e i n i t i a t e d , p o s s i b l y o r p h a n i n g t h e o r i g i n a l l o w e r p r i o r i t y t i m e r i n t e r r u p t . w o r k a r o u n d : w h e n u s i n g n e s t e d i n t e r r u p t s , a t t h e b e g i n n i n g o f t h e i n t e r r u p t r o u t i n e b e f o r e t h e g l o b a l i n t e r r u p t s are enabled w ith a cli, timer interrupts m u st be speci fica lly m aske d . at the end of the tim er i n terrupt routine b e i n g s e r v i c e d , y o u n e e d t o s e t t h e i n t e r r u p t e n a b l e b i t i n t h e p r o c e s s s t a t u s w o r d t o g l o b a l l y d i s a b l e i n t e r r u p t s p r i o r t o c l e a r i n g t h e t i m e r i n t e r r u p t b e i n g s e r v i c e d a n d u n m a s k t h e a p p r o p r i a t e t i m e r i n t e r r u p t s . 2 ) p r o b l e m : lock up just after reset is r e le ased. a n a l y s i s : u s u a l l y , t h e f i r s t i n s t r u ction is a long jum p to the start of the user' s code. in this case, the c o m p i l e r a p p a re n t l y i n s e rt e d a s h o rt j u m p i n s t ru c t i on with zero displacem e nt before the expected long j u m p i n s t ru c t i o n . t h e o e m d e v i c e s t u t t e re d , b u t r ecovered to execute the l o n g j u m p , w h i l e t h e i a device instruction pointer was corrupted, causing th e lock up. in summary, a short jum p with zero d i s p l a c e m e n t i s a c o r n e r c a s e t h a t does not work in the ia device. w o r k a r o u n d : d o n o t u s e a s h o r t j u m p i n s t r u c t i o n w i t h z e r o d i s p l a c e m e n t . 3 ) p r o b l e m : i n t e r m i t t e n t s t a r t u p . a n a l y s i s : p r o c e s s o r e i t h e r c a m e o u t of reset norm a lly, or would go into a series of watchdog tim eouts. the addition of 10k oh m pullups to the w r _n an d r d _ n o u t p u t s s e e m e d t o s o l v e t h e i s s u e . further analysis of the oem device shows the presence of undocum ented pullups on these pins, w h i c h w i l l p u l l t h e m h i g h w h e n t h e r e s e t c o n d i t i o n t r i s t a t e s t h e s e p i n s . t h e innovasic device does not include internal pullups on these pins allo wing these outputs to float during reset. w o r k a r o u n d : a d d 1 0 k o h m p u l l u p s t o w r _ n a n d r d _ n p i n s t o guarantee proper logic levels at the end of reset. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m
i a 1 8 6 e m / i a 1 8 8 e m data sh eet 8 / 1 6 - b i t m i c r o c o n t r o l l e r s a s o f p r o d u c t i o n v e r s i o n - 0 3 4) p r o b l e m : t i m e r o p e r a t i o n i n c o n t i n u o u s m o d e . analy s is the timers ( ti mer0 and tim e r1) do not f unction per th e specification when set in continuous mode with no external tim er input st imulus to initiate/continue count. workaround : none. 3 7 3 7 p r i n c e t o n n e , s t e 1 3 0 a l b u q u e r q u e , n m 8 7 1 0 7 t e l 5 0 5 . 8 8 3 . 5 2 6 3 f a x 5 0 5 . 8 8 3 . 5 4 7 7 w w w . i n n o v a s i c . c o m

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